On Mon, 06 Jan 2020 04:04:23 +0300, Dmitry Osipenko wrote: > It is more robust to check completion status in addition to the left time > in a case of DMA transfer because transfer's completion happens in two > phases [one is ISR, other is tasklet] and thus it is possible that DMA is > completed while I2C completion awaiting times out because of the deferred > notification done by the DMA driver. The DMA completion status becomes > 100% actual after DMA synchronization. This fixes spurious DMA timeouts > when system is under load. > > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> > --- > drivers/i2c/busses/i2c-tegra.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Tested-by: Thierry Reding <treding@xxxxxxxxxx>
