G'day All,
I'm seeing a problem with the designware driver in a multi-master system.
This is an Altera / Intel Cycloe V SoC.
This is with it connected to a ltc1760 sbs manager which acts as a slave and master.
What I'm seeing is that a requested read of the ltc1760 will return successfully before
the u2c transfer has been done. Read data contain garbage.
In i2c_dw_xfer() I set all read buffers to 0xff and get 0xffff as the return value
from sbsm_read_word().
I've injected a gpio trigger before and after the sbsm_read_word() call and
looked at the traffic in between. I can see the ltc1760 as master talking to
the sbs batteries and after the sbsm_read_word() call returns the start of the
actual sbsm_read_word() call is started with the address and and cmd byte being
sent on the wire. The bus then hangs with scl held low by the
designware driver, while I think it waits for the driver to start the read.
I've been able to isolate which device is driving the bus
by routing the i2c control signal thru the c-v fabric and tapping the OE enables from
the designware core to separate pins.
What I think is going on is the the stop events from the ltc1760 are being
counted by the driver as part of it's transaction.
ie in i2c_dw_irq_handler_master() the completion is only monitoring
if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) {
complete(&dev->cmd_complete);
Anyone have any thoughts on how to fix this?
Should complete only be called if DW_IC_INTR_RX_FULL or DW_IC_INTR_TX_EMPTY are
also set?
--
Regards
Phil Reid
