On Tue, Oct 16, 2018 at 12:01:48PM +0900, Masahiro Yamada wrote:
> Currently, a timeout error could happen at a repeated START condition.
>
> For a (non-repeated) START condition, the controller starts sending
> data when the UNIPHIER_FI2C_CR_STA bit is set. However, for a repeated
> START condition, the hardware starts running when the slave address is
> written to the TX FIFO - the write to the UNIPHIER_FI2C_CR register is
> actually unneeded.
>
> Because the hardware is already running before the IRQ is enabled for
> a repeated START, the driver may miss the IRQ event. In most cases,
> this problem does not show up since modern CPUs are much faster than
> the I2C transfer. However, it is still possible that a context switch
> happens after the controller starts, but before the IRQ register is
> set up.
>
> To fix this,
>
> - Do not write UNIPHIER_FI2C_CR for repeated START conditions.
>
> - Enable IRQ *before* writing the slave address to the TX FIFO.
>
> - Disable IRQ for the current CPU while queuing up the TX FIFO;
> If the CPU is interrupted by some task, the interrupt handler
> might be invoked due to the empty TX FIFO before completing the
> setup.
>
> Fixes: 6a62974b667f ("i2c: uniphier_f: add UniPhier FIFO-builtin I2C driver")
> Signed-off-by: Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx>
Applied to for-next, thanks!
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