Hi Phil, > > So, it is not possible to read SCL status then? Hmm, currently a working > > get_scl is required... ... > > Well, I don't know much about this IP core and how/where it is used. I > > just wonder what happens if another user comes along using an > > open-drain GPIO. Is that possible? > > > > I assume it is the same with SDA? Non open-drain? Output only? > > > > Just had a closer look at how it's setup here. > Maybe the following helps. Thanks for the detailed explanation. I am just afraid it is a litle too detailed for me. I am not sure if I can read it correctly: When you read the SCL/SDA GPIO, does it return the true state of the SCL/SDA line or does it just reflect the value it was set to output? > There's no concept of HiZ internally in the FPGA. Which probably means SDA is to be treated the same as SCL -> push/pull. > If there was some kinda of OpenDrain gpio driver that modelled a FET > driven by a push pull GPIO I guess it could be made to work. Still, that sounds quite unlikely to me, so we can for now assume that all designware users will have push/pull? Disclaimer: I have zero experience with this core, I don't know how hard it is to modify or which versions are out there. Thanks for your help, Wolfram
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