Stefan Wahren <stefan.wahren@xxxxxxxx> writes: > From: Eric Anholt <eric@xxxxxxxxxx> > > The CLKT register contains at poweron 0x40, which at our typical 100kHz > bus rate means .64ms. But there is no specified limit to how long devices > should be able to stretch the clocks, so just disable the timeout. We > still have a timeout wrapping the entire transfer. > > Signed-off-by: Eric Anholt <eric@xxxxxxxxxx> > Signed-off-by: Stefan Wahren <stefan.wahren@xxxxxxxx> > --- > Hi, > just like "i2c: bcm2835: Set up the rising/falling edge delays" this is a > outstanding bugfix. Unfortunately i only have I2C slaves, which doesn't > stretch the clock. So test feedback is very welcome. I also didn't have any particular devices that this fixed. It was just an issue that came up in a previous discussion of clock stretching.
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