On Fri, Jan 26, 2018 at 01:09:50PM +0100, Andrzej Hajda wrote:
> HSI2C_MASTER_ST_LOSE state is not documented properly, extensive tests
> show that hardware is usually able to recover from this state without
> interrupting the transfer. Moreover documentation says that
> such state can be caused by slave clock stretching, and should not be
> treated as an error during transaction. The only place it indicates
> an error is just before starting transaction. In such case bus recovery
> procedure should be performed - master should pulse SCL line nine times
> and then send STOP condition, it can be repeated until SDA goes high.
> The procedure can be performed using manual commands HSI2C_CMD_READ_DATA
> and HSI2C_CMD_SEND_STOP.
>
> Signed-off-by: Andrzej Hajda <a.hajda@xxxxxxxxxxx>
> ---
> Hi Wolfram,
>
> This patch integrates and invalidates my previous patches [1][2].
> I hope inline comments are sufficient.
Yes, they are. Thanks!
One minor thing, though:
> +static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c)
> +{
> + u32 val;
> +
> + dev_dbg(i2c->dev, "%s: start\n", __func__);
...
> + dev_dbg(i2c->dev, "%s: end\n", __func__);
This was probably useful for you but is not useful debug for upstream,
I'd think.
Rest looks good to me.
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