On Thu, Jan 04, 2018 at 06:18:13PM +0000, Radu Rendec wrote: > Use only a portion of the data buffer for DMA transfers, which is always > 16-byte aligned. This makes the DMA buffer address 16-byte aligned and > compensates for spurious hardware parity errors that may appear when the > DMA buffer address is not 16-byte aligned. > > The data buffer is enlarged in order to accommodate any possible 16-byte > alignment offset and changes the DMA code to only use a portion of the > data buffer, which is 16-byte aligned. > > The symptom of the hardware issue is the same as the one addressed in > v3.12-rc2-5-gbf41691 and manifests by transfers failing with EIO, with > bit 9 being set in the ERRSTS register. > > Signed-off-by: Radu Rendec <radu.rendec@xxxxxxxxx> Applied to for-next with Neil's ack, thanks!
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