On 05/18/2017 04:44 PM, Ard Biesheuvel wrote:
On 18 May 2017 at 14:05, Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx> wrote:
I have a fix for this. Could you try does it fix the issue for you?
http://www.spinics.net/lists/linux-i2c/msg29509.html
Thanks. But the question is really whether we want to change the
driver so that the DW_IC_SS_SCL_HCNT/DW_IC_SS_SCL_LCNT registers are
no longer programmed at all when running at a higher speed. Can you
guarantee that this will not cause any change in behavior in all
instances of this hardware that are supported currently, no matter how
they are synthesized and described to the OS? The previous commit only
affected the platdrv variety AFAIR
Obviously I cannot guarantee are there any side effects as I don't know
the IP. However I forgot one important point: high-speed transfers
always starts in fast-mode so those timing parameters too are needed
when bus is configured for high-speed. So best is to write all of them.
--
Jarkko
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