On Sun, 2016-06-19 at 19:42 +0200, Wolfram Sang wrote:
> On Wed, Jun 15, 2016 at 06:05:04PM +0300, Andy Shevchenko wrote:
> > Tested on bare metal (Intel Edison) by enumerating I2C GPIO
> > expanders.
> >
> > In v2:
> > - leave bus 3 at STD speed for Medfield
> > - be consistent with workflow, i.e. call ->setup, and _then_ assign
> > to i2c
> > properties
> > - add a comment to explain magic numbers for Merrifield
> > - add an Ack for patch 3
> >
> > Andy Shevchenko (3):
> > i2c: designware-pci: Make bus number allocation robust
> > i2c: designware-pci: Introduce Merrifield support
> > i2c: designware-pci: Sort header block alphabetically
> >
> > drivers/i2c/busses/i2c-designware-core.h | 1 +
> > drivers/i2c/busses/i2c-designware-pcidrv.c | 143 +++++++++++++++++-
> > -----------
> > 2 files changed, 86 insertions(+), 58 deletions(-)
>
> Applied to for-next, thanks!
Thanks.
Wolfram, just noticed that comment message in the second patch is not
fully clear. I would update it as follows
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -125,10 +125,10 @@ static int mfld_setup(struct pci_dev *pdev, struct
dw_pci_controller *c)
static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller
*c)
{
/*
- * On Intel Merrifield the i2c busses are enumerated [1..7]. So,
we add
- * 1 to shift the default range. Besides that the first PCI slot
- * provides 4 functions, that's why we have to add 0 to the head
slot
- * and 4 to the tail one.
+ * On Intel Merrifield the user visible i2c busses are
enumerated
+ * [1..7]. So, we add 1 to shift the default range. Besides that
the
+ * first PCI slot provides 4 functions, that's why we have to
add 0 to
+ * the fisrt slot and 4 to the next one.
*/
switch (PCI_SLOT(pdev->devfn)) {
case 8:
Should I send a new patch or you can fold it?
--
Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Intel Finland Oy
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