Hi On 05/23/2016 12:47 PM, Jean Delvare wrote:
Starting with the 8-Series/C220 PCH (Lynx Point), the SMBus controller includes a SPD EEPROM protection mechanism. Once the SPD Write Disable bit is set, only reads are allowed to slave addresses 0x50-0x57. However the legacy implementation of I2C Block Read since the ICH5 looks like a write, and is therefore blocked by the SPD protection mechanism. This causes the eeprom and at24 drivers to fail. So assume that I2C Block Read is implemented as an actual read on these chipsets. I tested it on my Q87 chipset and it seems to work just fine. Signed-off-by: Jean Delvare <jdelvare@xxxxxxx> Cc: Jarkko Nikula <jarkko.nikula@xxxxxxxxxxxxxxx> Cc: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> Cc: Wolfram Sang <wsa@xxxxxxxxxxxxx> --- Jarkko, Mika, that's what I'm using on my machine now. It works, but obviously I'd prefer to have confirmation from Intel hardware people that this is the right thing to do before it goes upstream.
I haven't yet found the contact but search is on going. -- Jarkko -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
