On Tue, Feb 10, 2015 at 04:46:33PM +0100, Valentin Longchamp wrote: > For the 85xx platforms, the source clock for the i2c-mpc can change from > one SoC to another. This is documented in the AN2919 "Determining the > I2C Frequency Divider Ratio for SCL" by Freescale. Not taking this into > account can lead to the output SCL frequency to by off by an offset. It > was observed on the P2041 from the QorIQ family. > > This patch fixes this problem by setting the prescaler value to the > appropriate value when required. The SoCs that required a different > prescaler than 1 are identified by reading out the SVR as discussed in > http://thread.gmane.org/gmane.linux.drivers.devicetree/94247/focus=20556 > > Signed-off-by: Valentin Longchamp <valentin.longchamp@xxxxxxxxxxx> > Applied to for-next, thanks!
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