Dear Wolfram, On Tue, 13 Jan 2015 06:36:54 -0800 Wolfram Sang <wsa@xxxxxxxxxxxxx> wrote: > > On Thu, Dec 11, 2014 at 02:26:41PM +0800, Jisheng Zhang wrote: > > readl/writel is too expensive especially on Cortex A9 w/ outer L2 cache. > > This introduces i2c read/write errors on Marvell BG2/BG2Q SoCs when there > > are heavy L2 cache maintenance operations at the same time. > > Reading this again, I got a question: > > Really read/write errors? I would think that there is a performance > penalty because of the memory barriers. But errors? I dunno whether I can call the issue as error. The situation is one i2c client has a bit strict timing requirement. Without the patch, if there are heavy L2 cache maintenance operations at the same time, there may be long delay between each DW_IC_DATA_CMD write opeartions in i2c_dw_xfer_msg() in the DW_IC_INTR_TX_EMPTY isr. Thus about 1/300 i2c transactions may be ignored by the i2c client per my test. > > > The driver does not perform DMA, so it's safe to use the relaxed version. > > From another side, the relaxed io accessor macros are available on all > > architectures now, so we can use the relaxed versions instead. > > Can the designware core make use of DMA in theory? > the IP can do DMA in theory. But currently, there's no DMA support in the driver. Thanks for your review, Jisheng -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
