On Thu, Dec 11, 2014 at 02:26:41PM +0800, Jisheng Zhang wrote: > readl/writel is too expensive especially on Cortex A9 w/ outer L2 cache. > This introduces i2c read/write errors on Marvell BG2/BG2Q SoCs when there > are heavy L2 cache maintenance operations at the same time. Reading this again, I got a question: Really read/write errors? I would think that there is a performance penalty because of the memory barriers. But errors? > The driver does not perform DMA, so it's safe to use the relaxed version. > From another side, the relaxed io accessor macros are available on all > architectures now, so we can use the relaxed versions instead. Can the designware core make use of DMA in theory?
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