Hi Uwe, On 11/23/2014 10:36 PM, Uwe Kleine-König wrote: > On Fri, Nov 21, 2014 at 09:33:22PM +0200, Grygorii Strashko wrote: >> On 11/21/2014 09:07 PM, Uwe Kleine-König wrote: >>> On Thu, Nov 20, 2014 at 12:03:07PM +0200, Grygorii Strashko wrote: >>> Just another general comment about the driver that doesn't influence the >>> correctness of this patch: The i2c-davinci driver is quite quick to >>> reset the bus. I wonder how often this reset triggers. Is the bus in >>> question less "stable" than others? >> >> In comparison to ..? :) > In comparison to other bus drivers in other SoCs. I know this might be > hard to answer. I just wonder where the reason for this has to be > located. Strange hardware? Software bug? Or is this SoC just operating > with strange slaves more often than others? Davinci driver does reset in two cases: - when I2C transaction isn't completed due to timeout (no irq received) - when BB is detected both cases are reasonable, because in 1st case HW state is undefined in 2d case - Davinci I2C supports only master mode and if BB detected we need perform some recovery procedure. Also, this patch doesn't introduce functional changes - it's just code reworking intended to reuse I2C bus recovery infrastructure i2c-omap.c - OMAP I2C driver does mostly the same now. i2c-tegra.c - seems, It will do reset even frequently. i2c-imx.c - if understand right, it will reinitialize I2C controller before each transfer, because it enables/disables I2C clocks. ... So, what i can say here is just "In comparison to ..?" :) regards, -grygorii -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
