On Fri, Nov 21, 2014 at 10:08:08AM -0600, Felipe Balbi wrote: > On Fri, Nov 21, 2014 at 01:28:43AM +0400, Alexander Kochetkov wrote: > > In a multimaster environment, after IP software reset, BB-bit value doesn't > > correspond to the current bus state. It may happen what BB-bit will be 0, > > while the bus is busy due to another I2C master activity. > > > > Any transfer started when BB=0 and bus is busy wouldn't be completed by IP > > and results in controller timeout. More over, in some cases IP could > > interrupt another master's transfer and corrupt data on wire. > > > > The commit implement method allowing to prevent IP from entering into > > "controller timeout" state and from "data corruption" state. > > > > The one drawback is the need to wait for 10ms before the first transfer. > > > > Tested on Beagleboard XM C. > > > > Signed-off-by: Alexander Kochetkov <al.kochet@xxxxxxxxx> > > Tested on BBB and AM437x Starter Kit > > Tested-by: Felipe Balbi <balbi@xxxxxx> > Reviewed-by: Felipe Balbi <balbi@xxxxxx> Huh, I can't apply this one? Which kernel version is this based on?
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