On Fri, Nov 07, 2014 at 12:10:44PM +0000, Andrew Jackson wrote: > If the Designware core is configured with IC_EMPTYFIFO_HOLD_MASTER_EN > set to zero, allowing the TX FIFO to become empty causes a STOP > condition to be generated on the I2C bus. If the transmit FIFO > threshold is set too high, an erroneous STOP condition can be > generated on long transfers - particularly where the interrupt > latency is extended. > > Signed-off-by: Andrew Jackson <Andrew.Jackson@xxxxxxx> > Signed-off-by: Liviu Dudau <Liviu.Dudau@xxxxxxx> Applied to for-current, thanks!
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