Hi, Jean Delvare: > If both pins can trigger an interrupt > when their level changes, we could use this feature I'm reasonably sure, thinking about this, that safe multimaster without interrupts on the data line (so that you can watch for Start and Stop conditions) is basically impossible. Not if you want your computer to do anything while it waits for the bus transaction to finish, that is. > Note that "one and a half clock period" is not something which > evaluates to a number. You have no idea at what frequency the other > master, if it exists, would be driving the bus. And the I2C > specification does not specify a minimum operating frequency, so in > theory you'd have to wait... forever. To solve this problem, SMBus > specifies a 50 µs maximum bus idle time (which corresponds to a 10 kHz > clock, the minimum allowed under SMBus.) I suppose this is a sane > setting in practice even for I2C controllers. It does evaluate to a number if we assume that there's no good reason for the Clock line to be High for much longer than 5µS, unless the bus is idle of course. Needless to say, there might be a number of *bad* reasons for that … > At the other end of the > spectrum, we have to deal with the maximum I2C frequency, 400 kHz in > our context. This means you can't have more than 1.25 µs between polls. Just wait until somebody implements Hs mode. :-P > In all cases we'll certainly want to let adapters tell whether they are > operating on a multi-master bus or not, so that the whole thing can be > disabled when not needed. They'll certainly notice that the first time they lose arbitration. -- -- Matthias Urlichs -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
