The PECI CPU sensors are available as soon as the CPU is powered, however the PECI DIMM sensors are available after DRAM has been trained and thresholds have been written by host firmware. The default timeout of 30 seconds isn't enough for modern multisocket platforms utilizing DDR5 memory to bring up the memory and enable PECI sensor data. Bump the default timeout to 10 minutes in case the system starts without cached DDR5 training data. Signed-off-by: Patrick Rudolph <patrick.rudolph@xxxxxxxxxxxxx> --- drivers/hwmon/peci/dimmtemp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c index 5ca4d04e4b14..4a72e9712408 100644 --- a/drivers/hwmon/peci/dimmtemp.c +++ b/drivers/hwmon/peci/dimmtemp.c @@ -47,7 +47,7 @@ #define GET_TEMP_MAX(x) (((x) & DIMM_TEMP_MAX) >> 8) #define GET_TEMP_CRIT(x) (((x) & DIMM_TEMP_CRIT) >> 16) -#define NO_DIMM_RETRY_COUNT_MAX 5 +#define NO_DIMM_RETRY_COUNT_MAX 120 struct peci_dimmtemp; -- 2.41.0
