On 4/8/2023 8:04 pm, Andrew Lunn wrote:
On Fri, Aug 04, 2023 at 04:45:22PM +0800, Choong Yong Liang wrote:
Intel platforms’ integrated Gigabit Ethernet controllers support
2.5Gbps mode statically using BIOS programming. In the current
implementation, the BIOS menu provides an option to select between
10/100/1000Mbps and 2.5Gbps modes. Based on the selection, the BIOS
programs the Phase Lock Loop (PLL) registers. The BIOS also read the
TSN lane registers from Flexible I/O Adapter (FIA) block and provided
10/100/1000Mbps/2.5Gbps information to the stmmac driver. But
auto-negotiation between 10/100/1000Mbps and 2.5Gbps is not allowed.
The new proposal is to support auto-negotiation between 10/100/1000Mbps
and 2.5Gbps . Auto-negotiation between 10, 100, 1000Mbps will use
in-band auto negotiation. Auto-negotiation between 10/100/1000Mbps and
2.5Gbps will work as the following proposed flow, the stmmac driver reads
the PHY link status registers then identifies the negotiated speed.
Based on the speed stmmac driver will identify TSN lane registers from
FIA then send IPC command to the Power Management controller (PMC)
through PMC driver/API. PMC will act as a proxy to programs the
PLL registers.
Have you considered using out of band for all link modes? You might
end up with a cleaner architecture, and not need any phylink/phylib
hacks.
Andrew
Hi Andrew,
After conducting a comprehensive study, it seems that implementing
out-of-band for all link modes might not be feasible. I may have missed
some key aspects during my analysis.
Would you be open to sharing a high-level idea of how we could potentially
make this feasible? Your insights would be greatly appreciated.
By the way, I've submitted a new design that not exposing phylink's AN mode
into phylib. Please help review it to determine if it is acceptable.
