On Wed, Nov 09, 2022 at 06:40:02PM +0100, Thierry Reding wrote: > On Tue, Nov 08, 2022 at 04:22:20PM +0200, Andy Shevchenko wrote: > > This is a continuation of the previously applied PWM LPSS cleanup series. > > Now, we would like to enable PWM optional feature that may be embedded > > into Intel pin control IPs (starting from Sky Lake platforms). > > > > I would like to route this via Intel pin control tree with issuing > > an immutable branch for both PINCTRL and PWM subsystems, but I'm > > open for other suggestions. > > I don't have any objections for this to go through the Intel tree as > long as Uwe is happy with this. So far Uwe acknowledged patch 2 only, hopefully he will have time to go thru the rest. > Most of this is just reworking existing > things and the stub additions look good to me, so: > > Acked-by: Thierry Reding <thierry.reding@xxxxxxxxx> Thank you! -- With Best Regards, Andy Shevchenko