Re: [PATCH 1/2] pinctrl: mediatek: common: add quirk for broken set/clr modes

[Linus Walleij <linus.walleij@xxxxxxxxxx>]

On Mon, May 30, 2022 at 2:35 PM Fabien Parent <fparent@xxxxxxxxxxxx> wrote:

> On MT8365, the SET/CLR of the mode is broken and some pin modes won't
> be set correctly. Add a quirk for such SoCs, so that instead of using
> the SET/CLR register use the main R/W register
> to read/update/write the modes.
>
> Signed-off-by: Fabien Parent <fparent@xxxxxxxxxxxx>

What is the state of this patch set? I see changes are requested by
Angelo, are they being addressed?

Yours,
Linus Walleij