From: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed.
Exising SCIF3 settings on IP3SR1 should be SCIF3_A,
and existing settings on scif3_xxx[] are for SCIF3.
This patch add missing SCIF3 settings on IP0SR1,
rename IP3SR1 settings to SCIF3_A,
add missing scif3_a_xxx[].
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 68 ++++++++++++++++++++------
1 file changed, 53 insertions(+), 15 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 8af0bc89d4e1..634ef17b76f0 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -289,11 +289,11 @@
/* SR1 */
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_A_N) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_A_N) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -319,11 +319,11 @@
#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP3SR1_3_0 FM(HRX3) FM(SCK3) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_19_16 FM(HTX3) FM(TX3) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_A_N) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_A_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR2 */
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -825,18 +825,23 @@ static const u16 pinmux_data[] = {
/* IP0SR1 */
PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A),
+ PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3),
PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_A_N),
+ PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3),
PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_A_N),
+ PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N),
PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A),
+ PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N),
PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
+ PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3),
PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
@@ -901,23 +906,23 @@ static const u16 pinmux_data[] = {
/* IP3SR1 */
PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
- PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3),
+ PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
- PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N),
+ PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_A_N),
PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
- PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N),
+ PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_A_N),
PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
- PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3),
+ PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
- PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3),
+ PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
/* IP0SR2 */
@@ -2228,6 +2233,29 @@ static const unsigned int scif3_ctrl_mux[] = {
RTS3_N_MARK, CTS3_N_MARK,
};
+/* - SCIF3_A ------------------------------------------------------------------ */
+static const unsigned int scif3_a_data_pins[] = {
+ /* RX3_A, TX3_A */
+ RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
+};
+static const unsigned int scif3_a_data_mux[] = {
+ RX3_A_MARK, TX3_A_MARK,
+};
+static const unsigned int scif3_a_clk_pins[] = {
+ /* SCK3_A */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int scif3_a_clk_mux[] = {
+ SCK3_A_MARK,
+};
+static const unsigned int scif3_a_ctrl_pins[] = {
+ /* RTS3_A_N, CTS3_A_N */
+ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
+};
+static const unsigned int scif3_a_ctrl_mux[] = {
+ RTS3_A_N_MARK, CTS3_A_N_MARK,
+};
+
/* - SCIF4 ------------------------------------------------------------------ */
static const unsigned int scif4_data_pins[] = {
/* RX4, TX4 */
@@ -2508,6 +2536,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif3_data),
SH_PFC_PIN_GROUP(scif3_clk),
SH_PFC_PIN_GROUP(scif3_ctrl),
+ SH_PFC_PIN_GROUP(scif3_a_data),
+ SH_PFC_PIN_GROUP(scif3_a_clk),
+ SH_PFC_PIN_GROUP(scif3_a_ctrl),
SH_PFC_PIN_GROUP(scif4_data),
SH_PFC_PIN_GROUP(scif4_clk),
SH_PFC_PIN_GROUP(scif4_ctrl),
@@ -2799,6 +2830,12 @@ static const char * const scif3_groups[] = {
"scif3_ctrl",
};
+static const char * const scif3_a_groups[] = {
+ "scif3_a_data",
+ "scif3_a_clk",
+ "scif3_a_ctrl",
+};
+
static const char * const scif4_groups[] = {
"scif4_data",
"scif4_clk",
@@ -2884,6 +2921,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif3_a),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif_clk),
--
2.25.1
[PATCH v3 13/21] pinctrl: renesas: r8a779g0: add missing SCIF3
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- Subject: [PATCH v3 13/21] pinctrl: renesas: r8a779g0: add missing SCIF3
- From: Kuninori Morimoto <kuninori.morimoto.gx@xxxxxxxxxxx>
- Date: Tue, 14 Jun 2022 06:00:00 +0000
- In-reply-to: <874k0nlrbw.wl-kuninori.morimoto.gx@renesas.com>
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- References:
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- From: Kuninori Morimoto
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