Hi Geert, Thank you for the review. On Mon, Jul 26, 2021 at 2:25 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > On Wed, Jul 21, 2021 at 9:16 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote: > > Add support for pin and gpio controller driver for RZ/G2L SoC. > > > > Based on a patch in the BSP by Hien Huynh <hien.huynh.px@xxxxxxxxxxx>. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > > Thanks for the update! > > > --- /dev/null > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > > > +#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH | \ > > + PIN_CFG_SR | \ > > + PIN_CFG_PUPD | \ > > + PIN_CFG_FILONOFF | \ > > + PIN_CFG_FILNUM | \ > > + PIN_CFG_FILCLKSEL) > > + > > +#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ > > + PIN_CFG_FILONOFF | \ > > + PIN_CFG_FILNUM | \ > > + PIN_CFG_FILCLKSEL) > > I thought you were going for MULTI? ;-) > I renamed it to _MULTI but it didn't sound good so renamed it to the other suggested alternative "MPXED". > > + > > +/* > > + * n indicates number of pins in the port, a is the register index > > + * and f is pin configuration capabilities supported. > > + */ > > +#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) > > +#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) >> 28) & 0x7) > > +#define RZG2L_GPIO_PORT_GET_INDEX(x) ((((x) & GENMASK(27, 20)) >> 20) & 0x7f) > > Actually the "& 0x7f" can be removed, too, if you adjust the mask: > > (((x) & GENMASK(26, 20)) >> 20) > Agreed. > > +#define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) > > + > > +/* > > + * BIT(31) indicates dedicated pin, p is the register index while > > + * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits > > + * (b * 8) and f is the pin configuration capabilities supported. > > + */ > > +#define RZG2L_SINGLE_PIN BIT(31) > > +#define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ > > + ((p) << 24) | ((b) << 20) | (f)) > > +#define RZG2L_SINGLE_PIN_GET_PORT(x) (((x) >> 24) & 0x7f) > > +#define RZG2L_SINGLE_PIN_GET_BIT(x) ((((x) & GENMASK(23, 20)) >> 20) & 0x7) > > Likewise: > > (((x) & GENMASK(22, 20)) >> 20) > Agreed. > > +#define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) > > > + struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); > > + struct function_desc *func; > > + unsigned int i, *psel_val; > > + struct group_desc *group; > > + unsigned long data; > > + int *pins; > > + > > + func = pinmux_generic_get_function(pctldev, func_selector); > > + if (!func) > > + return -EINVAL; > > + group = pinctrl_generic_get_group(pctldev, group_selector); > > + if (!group) > > + return -EINVAL; > > + > > + psel_val = func->data; > > + pins = group->pins; > > + data = (unsigned long)group->data; > > Lkp reports data is unused. > Which matches with passing NULL as the last parameter of > pinctrl_generic_add_group(). > Will drop this variable. Cheers, Prabhakar > > + > > + for (i = 0; i < group->num_pins; i++) { > > + dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", > > + RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]), > > + psel_val[i]); > > + rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), > > + RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]); > > + } > > + > > + return 0; > > +}; > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds