Hi Lars, On Wed, Feb 10, 2021 at 3:24 PM Lars Povlsen <lars.povlsen@xxxxxxxxxxxxx> wrote: > Geert Uytterhoeven writes: > > On Wed, Feb 10, 2021 at 3:17 PM Alexandre Belloni > > <alexandre.belloni@xxxxxxxxxxx> wrote: > >> On 10/02/2021 14:53:01+0100, Geert Uytterhoeven wrote: > >> > On Wed, Feb 10, 2021 at 2:45 PM Lars Povlsen <lars.povlsen@xxxxxxxxxxxxx> wrote: > >> > > Geert Uytterhoeven writes: > >> > > > the Microsemi/Microchip Serial GPIO device is present only Microsemi > >> > > > VCore III and Microchip Sparx5 SoCs. Hence add a dependency on > >> > > > ARCH_SPARX5 || SOC_VCOREIII, to prevent asking the user about this > >> > > > driver when configuring a kernel without support for these SoCs. > >> > > > > >> > > > Fixes: 7e5ea974e61c8dd0 ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO") > >> > > > Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > >> > > > --- > >> > > > drivers/pinctrl/Kconfig | 4 ++-- > >> > > > 1 file changed, 2 insertions(+), 2 deletions(-) > >> > > > > >> > > > diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig > >> > > > index 113073d5f89bbf70..3b75b1d7d3d1f1b0 100644 > >> > > > --- a/drivers/pinctrl/Kconfig > >> > > > +++ b/drivers/pinctrl/Kconfig > >> > > > @@ -353,8 +353,8 @@ config PINCTRL_OCELOT > >> > > > > >> > > > config PINCTRL_MICROCHIP_SGPIO > >> > > > bool "Pinctrl driver for Microsemi/Microchip Serial GPIO" > >> > > > - depends on OF > >> > > > - depends on HAS_IOMEM > >> > > > + depends on OF && HAS_IOMEM > >> > > > + depends on ARCH_SPARX5 || SOC_VCOREIII || COMPILE_TEST > >> > > > select GPIOLIB > >> > > > select GPIOLIB_IRQCHIP > >> > > > select GENERIC_PINCONF > >> > > > >> > > Thank you for your patch. Unfortunately, it makes it impossible to use > >> > > the driver across PCIe - which is a specifically desired configuration. > >> > > > >> > > Could you add CONFIG_PCI to the || chain? > >> > > >> > Sure. > >> > > >> > Is PCIe the only other transport over which the register can be accessed? > >> > Or can this also be done over e.g. SPI, like on Ocelot[1]? > >> > > >> > [1] https://lore.kernel.org/linux-gpio/20200511145329.GV34497@xxxxxxxxx/ > >> > > >> > >> Yes, this driver IP is also available on Ocelot (this is SOC_VCOREIII) > >> so this is also available over SPI. > > > > Hence would you consider > > > > depends on ARCH_SPARX5 || SOC_VCOREIII || PCI || SPI || COMPILE_TEST > > > > acceptable? Or would that be futile, as must systems have PCI and/or > > SPI enabled anyway? > > > > Gr{oetje,eeting}s, > > > > Geert > > Yes, that would be fine, but as you say - not have a lot of impact. > > Up to you... OK, I'll drop this. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds