Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support

[Hanks Chen <hanks.chen@xxxxxxxxxxxx>]

Hi all,

Gentle ping on this patch.

Thanks


Hanks Chen


On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote:
> Add MT6779 UART0 clock support.
> 
> Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
> Signed-off-by: Wendell Lin <wendell.lin@xxxxxxxxxxxx>
> Signed-off-by: Hanks Chen <hanks.chen@xxxxxxxxxxxx>
> Reviewed-by: Matthias Brugger <matthias.bgg@xxxxxxxxx>
> ---
>  drivers/clk/mediatek/clk-mt6779.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> index 9766cccf5844..6e0d3a166729 100644
> --- a/drivers/clk/mediatek/clk-mt6779.c
> +++ b/drivers/clk/mediatek/clk-mt6779.c
> @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
>  		    "pwm_sel", 19),
>  	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
>  		    "pwm_sel", 21),
> +	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> +		    "uart_sel", 22),
>  	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
>  		    "uart_sel", 23),
>  	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",