Re: [PATCH] pinctrl: cherryview: Associate IRQ descriptors to irqdomain manually

[Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>]

On Wed, 2018-04-25 at 13:32 +0300, Mika Westerberg wrote:
> When we dropped the custom Linux GPIO translation it resulted that the
> IRQ numbers changed slightly as well. Normally this would be fine
> because everyone is expected to use controller relative GPIO numbers
> and
> ACPI GpioIo/GpioInt resources. However, there is a certain set of
> Intel_Strago based Chromebooks where i8042 keyboard controller IRQ
> number is hardcoded be 182 (this is corrected with newer coreboot but
> the older ones still have the hardcoded Linux IRQ number). Because of
> this hardcoded IRQ number keyboard on those systems accidentally broke
> again.
> 
> Fix this by manually associating IRQ descriptors to the chip irqdomain
> so that there are no gaps on those systems. Other systems are not
> affected.
> 

Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>

> Fixes: 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux
> GPIO translation")
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=199463
> Reported-by: Sultan Alsawaf <sultanxda@xxxxxxxxx>
> Signed-off-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>
> ---
>  drivers/pinctrl/intel/pinctrl-cherryview.c | 16 ++++++++++++----
>  1 file changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c
> b/drivers/pinctrl/intel/pinctrl-cherryview.c
> index b1ae1618fefe..fee9225ca559 100644
> --- a/drivers/pinctrl/intel/pinctrl-cherryview.c
> +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
> @@ -1622,22 +1622,30 @@ static int chv_gpio_probe(struct chv_pinctrl
> *pctrl, int irq)
>  
>  	if (!need_valid_mask) {
>  		irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
> -						chip->ngpio,
> NUMA_NO_NODE);
> +						community->npins,
> NUMA_NO_NODE);
>  		if (irq_base < 0) {
>  			dev_err(pctrl->dev, "Failed to allocate IRQ
> numbers\n");
>  			return irq_base;
>  		}
> -	} else {
> -		irq_base = 0;
>  	}
>  
> -	ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, irq_base,
> +	ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
>  				   handle_bad_irq, IRQ_TYPE_NONE);
>  	if (ret) {
>  		dev_err(pctrl->dev, "failed to add IRQ chip\n");
>  		return ret;
>  	}
>  
> +	if (!need_valid_mask) {
> +		for (i = 0; i < community->ngpio_ranges; i++) {
> +			range = &community->gpio_ranges[i];
> +
> +			irq_domain_associate_many(chip->irq.domain,
> irq_base,
> +						  range->base, range-
> >npins);
> +			irq_base += range->npins;
> +		}
> +	}
> +
>  	gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,
>  				     chv_gpio_irq_handler);
>  	return 0;

-- 
Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Intel Finland Oy
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