On Fri, Mar 16, 2018 at 10:02:09PM +0800, Icenowy Zheng wrote: > The Allwinner H6 SoC have its pin controllers with the first IRQ-capable > GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. > > Change the current code that uses IRQ bank base to a IRQ bank map, in > order to support the case that holes exist among IRQ banks. > > Signed-off-by: Icenowy Zheng <icenowy@xxxxxxx> Acked-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxx> Thanks! Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com
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