Le lun. 5 mars 2018 à 3:29, Ezequiel Garcia
<ezequiel@xxxxxxxxxxxxxxxxxxxx> a écrit :
On 4 March 2018 at 21:01, Paul Cercueil <paul@xxxxxxxxxxxxxxx> wrote:
Hi,
Le 2018-03-04 22:15, Ezequiel Garcia a écrit :
This commit fixes the values for the pins and functions
of mmc0 and mmc1, for JZ4770 and JZ4780 SoCs.
The bug was found on a Ci20 board, so changes are partially
tested on this board, in addition to careful verification
with the programming manual.
Cc: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
Signed-off-by: Ezequiel Garcia <ezequiel@xxxxxxxxxxxxxxxxxxxx>
The current values were obviously tested and do work with the CI20
(jz4780)
and the GCW0 (which has a jz4770).
Of course, maybe it's something else.
I've pushed a branch with MMC supported forwared-ported
to current mainline, in case you feel like giving a try.
It wasn't working for me, and this commit fixed it.
http://git.infradead.org/users/ezequielg/linux/shortlog/refs/heads/ci20-mmc-for-4.15
Looking at the JZ4780 PM pdf, I don't think any of your values are
correct.
For instance, you set:
static int jz4770_mmc0_1bit_a_pins[] = { 0x18, 0x19, 0x20, };
This means pins GPA24, GPA25 and GPB0.
Doh, of course. My changes to the PA muxing are just bullshit.
According to the manual, GPA24 is for
MMC0 reset, but the other two are not in any way related to the MMC
hardware.
Let's look a those that were actually tested. For instance:
-static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
+static int jz4770_mmc0_4bit_e_pins[] = { 0x94, 0x95, 0x96, 0x97,
0x9c,
0x9d };
IIUC, the driver is muxing pins PE21, PE22 and PE23, which
belong to msc0_d1, msc0_d2 and msc0_d3.
According to my spec, it should mux PE20, PE21, PE22, PE23,
PE28 and PE29 (d0, d1, d2, d3, clk, cmd). Which is what my
patch is trying to do, if I did the math right.
I'm confused about the fact that a 4-bit mode muxes
just three pins, instead of six. So what am I missing here?
The jz4770_mmc0_1bit_e_pins[] contains the pins required for doing *at
least*
1-bit I/O. The jz4770_mmc0_4bit_e_pins[] contains the *additional* pins
required to do 4-bit I/O.
In your devicetree, if you plan to use 4-bit I/O, you must enable the
two
groups:
pins_mmc0_4bit: mmc0-4bit {
function = "mmc0";
groups = "mmc0-1bit-e", "mmc0-4bit-e";
bias-disable;
};
Thanks,
--
Ezequiel García, VanguardiaSur
www.vanguardiasur.com.ar
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