On Mon, Jul 31, 2017 at 8:21 AM, Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx> wrote: > For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are > located across multiple registers. So, the register offset must be > taken into account. Otherwise, wrong input-enable status is displayed. > > While we here, rename the macro because it is a base address. > > Fixes: aa543888ca8c ("pinctrl: uniphier: support per-pin input enable for new SoCs") > Signed-off-by: Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx> Patch applied. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html