Re: [PATCH 1/5] pintrl: meson: add interrupts to pinctrl data

[Linus Walleij <linus.walleij@xxxxxxxxxx>]

On Sun, May 7, 2017 at 6:34 PM, Heiner Kallweit <hkallweit1@xxxxxxxxx> wrote:

> From: Jerome Brunet <jbrunet@xxxxxxxxxxxx>
> Add GPIO interrupt information to pinctrl data. Added to the original
> version from Jerome was data for Meson GXL.
>
> Signed-off-by: Jerome Brunet <jbrunet@xxxxxxxxxxxx>
> Signed-off-by: Heiner Kallweit <hkallweit1@xxxxxxxxx>

So what this does is:

> diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
> index 1aa871d5..890f296f 100644
> --- a/drivers/pinctrl/meson/pinctrl-meson.h
> +++ b/drivers/pinctrl/meson/pinctrl-meson.h
> @@ -81,6 +81,7 @@ enum meson_reg_type {
>   * @name:      bank name
>   * @first:     first pin of the bank
>   * @last:      last pin of the bank
> + * @irq:       hwirq base number of the bank
>   * @regs:      array of register descriptors
>   *
>   * A bank represents a set of pins controlled by a contiguous set of
> @@ -92,6 +93,8 @@ struct meson_bank {
>         const char *name;
>         unsigned int first;
>         unsigned int last;
> +       int irq_first;
> +       int irq_last;
>         struct meson_reg_desc regs[NUM_REG];
>  };

... adds a per-bank parent IRQ.

I am just discussing with Thierry that I would like to see some code
in the gpiolib core to deal with this mapping so we don't have to do a
whole lot of custom back mapping between parent IRQs and cascaded
IRQ in every driver that has a multiple-bank concept.

Please contribute to the discission, see thread subject:
"[PATCH v2] gpio: Add Tegra186 support"

Yours,
Linus Walleij
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