Re: [PATCH v2] gpio: pl061: use all specified IRQs for chained handler

[Linus Walleij <linus.walleij@xxxxxxxxxx>]

On Thu, Feb 23, 2017 at 1:58 PM, Sławomir Stępień (Nokia - PL/Wroclaw)
<slawomir.stepien@xxxxxxxxx> wrote:
> On Feb 23, 2017 10:45, Linus Walleij wrote:
>> On Wed, Feb 22, 2017 at 1:57 PM, Alexander Sverdlin
>> <alexander.sverdlin@xxxxxxxxx> wrote:
>>
>> >> - If the component has 8 IRQ lines, create a hierarchical IRQdomain
>> >>   and chip using a gpiolib core helper.
>> >
>> > This was an option of course, the only this is, PL061 spec says, there is
>> > GPIOINTR and if someone has forgot it, we can support it with a quirk.
>>
>> I don't know about that. The PL061 manual says:
>>
>> "The contents of this register are made available externally through the
>> intra-chip (or on-chip) GPIOMIS[7:0] signals."
>>
>> They don't say why, but it is reasonable to assume that this is an
>> either-or not both-and integration point.
>>
>> EITHER you route GPIOMIS[7:0] to individual IRQ lines to the CPU
>> OR you route GPIOINTR to the CPU.
>
> On page 2-10, 2.3.4 you can read:
>
> "a single interrupt output GPIOINTR and/or the individual interrupts can be
> sent to the interrupt controller."
>
> Also see figure 2-1, 4-2.
>
> Does it not says that there are two independent options available?

Ah I didn't see that. It just underscores the point even more :)

Anyways, from a software point of view you will want to either use
the individual IRQ lines *or* the aggregated IRQ line. Not both
at the same time (no usecase I can think of atleast).

Yours,
Linus Walleij
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