Hi Linus,
On Friday 15 April 2016 07:29 PM, Laxman Dewangan wrote:
On Friday 15 April 2016 07:33 PM, Linus Walleij wrote:
On Fri, Apr 15, 2016 at 1:47 PM, Laxman Dewangan
<ldewangan@xxxxxxxxxx> wrote:
On Friday 15 April 2016 04:45 PM, Linus Walleij wrote:
On Fri, Apr 15, 2016 at 11:55 AM, Laxman Dewangan
<ldewangan@xxxxxxxxxx>
wrote:
But to be sure we would like to know what is actually happening,
electronically speaking, when you set this up. Do you have any
idea?
From electronic point of view, the value of VIL, VIH, VOL, VOH
(Input/output
voltage level for low and high state) are different when talking for
0 t
1.8V and 0 to 3.3V.
Yeah that I get. But since it is switched on a per-pin basis, and
this is not about what voltage is actually supplied to the I/O cell,
because that comes from the outside, it is a mystery why it is
even needed.
I understand that there is a bit selecting driving voltage level in
the register range, what I don't understand is what that is
doing in the I/O cell.
The bit in the register must be routed to somehing in the I/O cell
and I would like to know what. I take it that an ordinary CMOS
totem-pole push-pull output is going to work the same with 1.8
and 3.3V alike so it's obviously not enabling any extra transistors
or anything.
I dont have answer for this now and I need to discuss with HW team to
get this info.
I will be back here after discussion with HW team.
I had discussion with HW team to get this info from analog point of view.
The IO circuitry has to be configured correctly to engage the right
level shifting circuits between the IO rail and the core voltage rail in
each direction; and that is the main purpose of this configuration. You
are correct, the output drivers will naturally drive towards the rails,
whatever their voltage may be; and the input receiver will likewise
reference itself naturally to the rail, although the switching threshold
of the receiver transistors may sometimes need configuration too.
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