Re: [PATCH v2] pinctrl: zynq: configure SPI SSx pins separately

[Sören Brinkmann <soren.brinkmann@xxxxxxxxxx>]

On Sun, 2015-04-26 at 11:32AM +0200, Helmut Buchsbaum wrote:
> Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI
> interfaces, SS0, SS1 and SS2 have to be configured separately as they may
> be used as simple GPIO lines.
> 
> This, of course, has to be considered in the devicetree, so pin controller
> configuration for e.g. an SPI0 using SS0 and SS1 only might look like the
> following snippet (derived from the example of chapter "17.5.3
> MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used
> as GPIO instead of being occupied by SPI0 SS2 function. Note the separate
> pinmux function for the slave select signals:
> 
> pinctrl_spi0_default: spi0-default {
> 	mux_spi {
> 		function = "spi0";
> 		groups = "spi0_0_grp";
> 	};
> 
> 	mux_ss {
> 		function = "spi0_ss";
> 		groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp";
> 	}
> 
> 	conf-output {
> 		pins = "MIO16", "MIO21";
> 		slew-rate = <0>;
> 		bias-disable;
> 		low-power-disable;
> 		io-standard = <1>;
> 	};
> 
> 	conf-input {
> 		pins = "MIO17";
> 		slew-rate = <0>;
> 		bias-high-impedance;
> 		low-power-disable;
> 		io-standard = <1>;
> 	};
> 
> 	conf-select {
> 		pins = "MIO18", "MIO19";
> 		slew-rate = <0>;
> 		bias-pull-up;
> 		low-power-disable;
> 		io-standard = <1>;
> 	};
> };
> 
> pinctrl_gpio0_default {
> 	mux {
> 		function = "gpio0";
> 		groups = "gpio0_20_grp"
> 	};
> 
> 	conf {
> 		pins = "MIO20";
> 		slew-rate = <0>;
> 		bias-pull-up;
> 		low-power-disable;
> 		io-standard = <1>;
> 	};
> };
> 
> Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@xxxxxxxxx>
Acked-by: Sören Brinkmann <soren.brinkmann@xxxxxxxxxx>

> ---

For future reference, please keep a changelog here when sending another
iteration of a patch.

	Regards,
	Sören

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