On Tue, Oct 10, 2023 at 05:37:43AM +0000, Manne, Nava kishore wrote: > Hi Yilun, > > Thanks for providing the review comments. > Please find my response inline. > > > -----Original Message----- > > From: Xu Yilun <yilun.xu@xxxxxxxxxxxxxxx> > > Sent: Saturday, October 7, 2023 12:47 PM > > To: Manne, Nava kishore <nava.kishore.manne@xxxxxxx> > > Cc: mdf@xxxxxxxxxx; hao.wu@xxxxxxxxx; yilun.xu@xxxxxxxxx; > > trix@xxxxxxxxxx; linux-fpga@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > > Pandey, Radhey Shyam <radhey.shyam.pandey@xxxxxxx> > > Subject: Re: [PATCH] fpga: versal: Add support for 44-bit DMA operations > > > > On Tue, Oct 03, 2023 at 12:44:09PM +0530, Nava kishore Manne wrote: > > > The existing implementation support only 32-bit DMA operation. > > > So, it fails to load the bitstream for the high DDR designs(Beyond 4GB). > > > To fix this issue update the DMA mask handling logic to support 44-bit > > > > This is the HW defined DMA addressing capability. Does the device only > > support up to 44 bits DMA? Any Doc? > > > The versal platform supports a maximum physical address size is 44-bit in AArch64. > For more details, please refer the Versal TRM (Memory space- section): > https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/Memory-Space Acked-by: Xu Yilun <yilun.xu@xxxxxxxxx> Applied. > > Regards, > Navakishore. >
