On Tue, Oct 03, 2023 at 12:44:09PM +0530, Nava kishore Manne wrote:
> The existing implementation support only 32-bit DMA operation.
> So, it fails to load the bitstream for the high DDR designs(Beyond 4GB).
> To fix this issue update the DMA mask handling logic to support 44-bit
This is the HW defined DMA addressing capability. Does the device
only support up to 44 bits DMA? Any Doc?
Thanks,
Yilun
> DMA operations.
>
> Signed-off-by: Nava kishore Manne <nava.kishore.manne@xxxxxxx>
> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xxxxxxx>
> ---
> drivers/fpga/versal-fpga.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> index e1601b3a345b..3710e8f01be2 100644
> --- a/drivers/fpga/versal-fpga.c
> +++ b/drivers/fpga/versal-fpga.c
> @@ -48,7 +48,7 @@ static int versal_fpga_probe(struct platform_device *pdev)
> struct fpga_manager *mgr;
> int ret;
>
> - ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
> + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
> if (ret < 0) {
> dev_err(dev, "no usable DMA configuration\n");
> return ret;
> --
> 2.25.1
>
