On Fri, 18 Nov 2022, Mark Brown wrote: > On Fri, Nov 18, 2022 at 02:49:45PM +0200, Ilpo Järvinen wrote: > > On Thu, 17 Nov 2022, Mark Brown wrote: > > > > No, what I'm objecting to there is pretty much the same thing I'm > > > saying here - this doesn't seem like it's a particularly generic > > > implementation and I'm really not clear that there'd be anything > > > meaningful left by the time the implementation assumptions are > > > removed. > > > That's probably because it sounds to me you're trying to extend its > > genericness beyond the domain where it's generic. That is, you're looking > > for genericness outside of IPs (that have their own driver each) in Intel > > FPGA domain. > > This just says it's adding "indirect regmap support" - there's > nothing here saying that it's some Intel specific thing but it's > quite specific to some IPs. Yeah, but it's that way mainly because of your earlier comments. :-) I tried to make it more "generic" to the extent possible because of your concern related to genericness and I therefore intentionally put the Intel specific numbers into the other change. Previously you were against saying it clearly that it's Intel FPGA specific when Matthew proposed changing the name to not sound something too generic. If you're ok with that now, I'm happy to make such change. > Perhaps you have some name for this > interface? You're only adding one user here which isn't helping > make the case that this is something generic. > > > Please also keep in mind that we're talking about an FPGA device here, a > > device that is capable of implementing other devices that fall under > > various drivers/xx/. Obviously each would have a driver of their own so > > there is no as strong only single device/driver mapping here as you might > > be thinking. > > I can't tell what you're trying to say here. Are you saying that > this is somehow baked into some FPGA design so that it's memory > mapped with only a few registers showing to the rest of the > system rather than just having a substantial memory mapped > window like is typically used for FPGAs, but someohow this > register window stuff is implemented in the soft IP so people are > just throwng vaugely similar interfaces into a random host mapped > register layout? What I tried to say the users are not expected to be nicely confined into drivers/mfd/ (and a single driver in there). You didn't answer at all my question about where to place the code? I'm repeating it with the context below since you cut it off: That's probably because it sounds to me you're trying to extend its genericness beyond the domain where it's generic. That is, you're looking for genericness outside of IPs (that have their own driver each) in Intel FPGA domain. Whether that is "generic" enough to reside in drivers/base/regmap can of course be debated but lets say I put it into drivers/mfd/ along with the code currently using it. By doing that, we'll postpone this discussion to the point when the first driver using it outside of drivers/mfd/ comes by. At that point, having the indirect code in drivers/mfd/ is shown to be a wrong choice. It's of course nothing that couldn't be fixed by patches moving the code around to some more preferred location. And that location likely turns out to be drivers/base/regmap, no? Or do you have a better place for it in that case? -- i.
