On Fri, Nov 18, 2022 at 02:49:45PM +0200, Ilpo Järvinen wrote: > On Thu, 17 Nov 2022, Mark Brown wrote: > > No, what I'm objecting to there is pretty much the same thing I'm > > saying here - this doesn't seem like it's a particularly generic > > implementation and I'm really not clear that there'd be anything > > meaningful left by the time the implementation assumptions are > > removed. > That's probably because it sounds to me you're trying to extend its > genericness beyond the domain where it's generic. That is, you're looking > for genericness outside of IPs (that have their own driver each) in Intel > FPGA domain. This just says it's adding "indirect regmap support" - there's nothing here saying that it's some Intel specific thing but it's quite specific to some IPs. Perhaps you have some name for this interface? You're only adding one user here which isn't helping make the case that this is something generic. > Please also keep in mind that we're talking about an FPGA device here, a > device that is capable of implementing other devices that fall under > various drivers/xx/. Obviously each would have a driver of their own so > there is no as strong only single device/driver mapping here as you might > be thinking. I can't tell what you're trying to say here. Are you saying that this is somehow baked into some FPGA design so that it's memory mapped with only a few registers showing to the rest of the system rather than just having a substantial memory mapped window like is typically used for FPGAs, but someohow this register window stuff is implemented in the soft IP so people are just throwng vaugely similar interfaces into a random host mapped register layout? Whatever's going on here this clearly isn't a generic implementation of an indirect register map.
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