As a résumé of this discussion I feel that it would be very viable to to
a commercial or non-commercial project that allows for easy use of a
single (or even multiple ) dedicated AMP CPU(s) working together with an
SMP Linux system in a multi core ARM Cortex A9 chip.
Here the supplier would need to provide:
- means to dedicate one (or more) CPU(s) to an AMP system(s)
(including setting the AMP Bit to prevent 1st level cache
synchronization for this CPU(s), and possibly including a patch for the
scheduler that performance prevents degradation due to the count of
managed CPUs being not identical with those found in hardware)
- means for communication with the AMP system(s) (i.e. a prototype for
a Kernel driver that allows for bidirectional "message-queue"- / pipe-
like communication using a DMA-alike non-cached memory region and mutual
interrupts for notification
- means to load and start a program in an AMP system (supposedly
provided by the same Kernel driver). Here supposedly some kind of cache
flush needs to be done as the cache synchronization is switched off for
the AMP CPU(s).
- appropriate documentation (including a definition on how to do the
software for the AMP system and including hints on how to calculate the
max latency)
What do you think ?
-Michael
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