Yesterday I have my first DVB-S2-streams with the TT3200.
Sources
- Manus snapshot at http://jusst.de/manu/stb0899-v4l-dvb.tar.bz2
- the szap-sources from http://dev.kewl.org/tmp/hvr4000/szap2.tgz
Envoirenment
- TT3200 (SAA7146AH, STB0899 C2L, STB6100, LNBP21 PD, 27000 MHz, board B2S3000 Rev 1.0 TT2006.1)
=> may be that the skystar HD is worked like TT3200 with that patch
- Tested succesfully with
=> Linux-Kernel 2.6.16-45 (from kernel.org)
=> 2.6.17-chw-8 (MythTV R5D1) and
=> 2.6.21.1 (from kernel.org)
- 32-bit-CPU (Pentium 4, 2.8 GHz with Hyperthreading) => Have no 64-bit- and no SMP-system!
Procedure for compiling and loading of drivers
- unpack kernel-sources (to /usr/src/linux) if necessary
- kernelsources should be builded ?!?
- unpack v4l-dvb-sources (to /usr/src/v4l-dvb)
- unpack szap2-sources (to /usr/src/szap)
- change to /usr/src/szap
- make
- make install
- check if szap2 is installed now
- change to /usr/src
- store attached patchfile as tt3200.diff
- patch the tree: patch -p0 <tt3200.diff
- change to /usr/src/v4l-dvb
- delete file /usr/src/v4l-dvb/v4l/.version
- make script-file executable: chmod +x v4l-scripts-make_myconfig.pl
- execute script-file: ./v4l-scripts-make_myconfig.pl
- make
- unload all dvb-driver: make rmmod
- install new dvb-driver: make install
- activate tt3200-driver: modprobe budget-ci
- change channels by:
szap2 -p -t0 xxx (for DVB-S-channels)
szap2 -p -t2 xxx (for DVB-S2-channels)
you need a file channels.conf under /homedir/.szap
- when you see that channel has locked, you can
create a file with: cat /dev/dvb/adapter0/dvr0
or watch witch mplayer: mplayer -fs /dev/dvb/adapter0/dvr0
Problems and notes:
- With this patch the TT3200 is build into modules budget-ci (thanks for hints and code of Marco).
- With this patch you can use your old tools like szap and dvbtune for DVB-S-channels (I dont now if it is a target for linuxtv).
- The tuning of TT3200 is not very stable with that driver (but much more better then with first patch).
=> One change is a patch in modul STB6100.c I get from Marco (Wait timed for lock of tuner, I only had used wait here).
=> Another is trying tune more than ones (it helps for DVB-S and DVB-S2).
=> The next is a ugly hack in stb0899_dvbs_algo (dont switch off the carrier detector for some channels)
=> The last is a ugly hack in stb0899_dvbs2_algo (something with inversion must be different between KNC1 and TT3200).
=> The tuning of KNC1-DVBS2-board is much more stable like with TT3200.
=> May be that there is someting wrong in the tunermodul and/or changings in interface between STB0899 and tunermodul?
- Sometimes you need to reactivate driver to get it work (rmmmod budget-ci + modprobe budget-ci).
=> I have see the same for KNC1-DVBS2-board when the tuner is not used for some seconds.
- With this patch two special things for TT3200 (ugly hacks) are build in modul stb0899_algo.c.
=> I cannot be part of stable code!!!
=> It is possible that problems on KNC1-DVBS2-board occures with that hacks.
=> One is that for some channels (e.g. Pro7) the carrier detector are not switched off at the end of tuning.
=> This has the effect that the TT3200 can lock this channels but I think there are instabilities in video then.
=> The second is that I can only get DVB-S2-channels with forcing AUTOINVERSION in stb0899_dvbs2_algo.
=> Both are marked with TODO.
- There must be effects on 64-bit- and or SMP-machines, that the drivers dont run successfully.
=> see e.g. http://www.linuxtv.org/pipermail/linux-dvb/2007-May/017959.html
I bought a KNC1-DVBS2-board and the tuning of DVB-S- and DVB-S2-channels is many much more stable as for TT3200. So I think I will use this board for my next tests (with mythtv) and may be wait until getting the TT3200-support in manus sources.
Regards.
diff -urNp v4l-dvb.org/linux/drivers/media/dvb/dvb-core/dvb_frontend.c v4l-dvb/linux/drivers/media/dvb/dvb-core/dvb_frontend.c
--- v4l-dvb.org/linux/drivers/media/dvb/dvb-core/dvb_frontend.c 2007-02-24 11:57:13.000000000 +0100
+++ v4l-dvb/linux/drivers/media/dvb/dvb-core/dvb_frontend.c 2007-05-21 19:16:42.000000000 +0200
@@ -460,8 +460,8 @@ int newapi_to_olddrv(struct dvbfe_params
case DVBFE_DELSYS_DVBS2:
case DVBFE_DELSYS_DSS:
case DVBFE_DELSYS_DVBH:
- printk("%s: SORRY ! Backward compatibility unavailable for these delivery systems !!\n", __func__);
- break;
+/* printk("%s: SORRY ! Backward compatibility unavailable for these delivery systems !!\n", __func__);
+*/ break;
default:
dprintk("%s: Unsupported delivery system\n", __func__);
return -EINVAL;
@@ -1559,10 +1559,20 @@ static int dvb_frontend_ioctl(struct ino
struct dvb_frontend_tune_settings fetunesettings;
fe->legacy = 1;
+
+ memset(&fepriv->fe_info, 0, sizeof (struct dvbfe_info));
+ fepriv->fe_info.delivery = DVBFE_DELSYS_DVBS;
+ fe->ops.get_info(fe, &fepriv->fe_info);
+
memcpy(&fepriv->parameters, parg, sizeof (struct dvb_frontend_parameters));
memset(&fetunesettings, 0, sizeof(struct dvb_frontend_tune_settings));
memcpy(&fetunesettings.parameters, parg, sizeof (struct dvb_frontend_parameters));
+ olddrv_to_newapi(fe,&fepriv->fe_params, &fepriv->parameters, FE_QPSK);
+
+ /* Request the search algorithm to search */
+ fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN;
+
/* force auto frequency inversion if requested */
if (dvb_force_auto_inversion) {
fepriv->parameters.inversion = INVERSION_AUTO;
@@ -1710,8 +1720,8 @@ static int dvb_frontend_ioctl(struct ino
fepriv->min_delay = (dvb_override_tune_delay * HZ) / 1000;
fepriv->state = FESTATE_RETUNE;
- printk("%s: FESTATE_RETUNE: fepriv->state=%d\n", __func__, fepriv->state);
- dvb_frontend_wakeup(fe);
+/* printk("%s: FESTATE_RETUNE: fepriv->state=%d\n", __func__, fepriv->state);
+*/ dvb_frontend_wakeup(fe);
dvb_frontend_add_event(fe, 0);
fepriv->status = 0;
err = 0;
@@ -1737,8 +1747,8 @@ static int dvb_frontend_ioctl(struct ino
}
break;
case DVBFE_GET_INFO:
- printk("%s: DVBFE_GET_INFO\n", __func__);
- fe->legacy = 0;
+/* printk("%s: DVBFE_GET_INFO\n", __func__);
+*/ fe->legacy = 0;
if (fe->ops.get_info) {
memcpy(&fepriv->fe_info, (struct dvbfe_info *) parg, sizeof (struct dvbfe_info));
err = fe->ops.get_info(fe, &fepriv->fe_info);
@@ -1893,13 +1903,15 @@ void dvb_frontend_detach(struct dvb_fron
{
void *ptr;
- if (fe->ops.release_sec) {
+ ptr = (void*)fe->ops.release_sec;
+ if (ptr) {
fe->ops.release_sec(fe);
- symbol_put_addr(fe->ops.release_sec);
+ symbol_put_addr(ptr);
}
- if (fe->ops.tuner_ops.release) {
+ ptr = (void*)fe->ops.tuner_ops.release;
+ if (ptr) {
fe->ops.tuner_ops.release(fe);
- symbol_put_addr(fe->ops.tuner_ops.release);
+ symbol_put_addr(ptr);
}
ptr = (void*)fe->ops.release;
if (ptr) {
diff -urNp v4l-dvb.org/linux/drivers/media/dvb/frontends/lnbp21.c v4l-dvb/linux/drivers/media/dvb/frontends/lnbp21.c
--- v4l-dvb.org/linux/drivers/media/dvb/frontends/lnbp21.c 2007-02-22 14:20:08.000000000 +0100
+++ v4l-dvb/linux/drivers/media/dvb/frontends/lnbp21.c 2007-05-21 19:16:42.000000000 +0200
@@ -127,6 +127,8 @@ struct dvb_frontend *lnbp21_attach(struc
/* override frontend ops */
fe->ops.set_voltage = lnbp21_set_voltage;
fe->ops.enable_high_lnb_voltage = lnbp21_enable_high_lnb_voltage;
+
+ printk("%s: Attaching LNBP21\n",__func__);
return fe;
}
diff -urNp v4l-dvb.org/linux/drivers/media/dvb/frontends/stb0899_algo.c v4l-dvb/linux/drivers/media/dvb/frontends/stb0899_algo.c
--- v4l-dvb.org/linux/drivers/media/dvb/frontends/stb0899_algo.c 2007-02-24 13:13:55.000000000 +0100
+++ v4l-dvb/linux/drivers/media/dvb/frontends/stb0899_algo.c 2007-05-21 20:54:28.000000000 +0200
@@ -519,6 +519,7 @@ enum stb0899_status stb0899_dvbs_algo(st
u8 eq_const[10];
s32 clnI = 3;
u32 bandwidth = 0;
+ s32 retry = 0;
/* BETA values rated @ 99MHz */
s32 betaTab[5][4] = {
@@ -596,9 +597,12 @@ enum stb0899_status stb0899_dvbs_algo(st
stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
-
+
stb0899_first_subrange(state);
do {
+ retry = 0;
+ do
+ {
/* Initialisations */
cfr[0] = cfr[1] = 0;
stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */
@@ -668,8 +672,11 @@ enum stb0899_status stb0899_dvbs_algo(st
}
}
}
- }
- if (internal->status != RANGEOK)
+ }
+ }
+ while ( ++retry < 5 && (internal->status != RANGEOK) );
+
+ if (internal->status != RANGEOK)
next_sub_range(state);
} while (internal->sub_range && internal->status != RANGEOK);
@@ -681,6 +688,7 @@ enum stb0899_status stb0899_dvbs_algo(st
/* if locked and range ok, set Kdiv */
if (internal->status == RANGEOK) {
dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
+
stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
@@ -734,11 +742,25 @@ enum stb0899_status stb0899_dvbs_algo(st
STB0899_SETFIELD_VAL(FRESRS, reg, 0);
stb0899_write_reg(state, STB0899_TSTRES, reg);
- /* disable carrier detector */
- reg = stb0899_read_reg(state, STB0899_CFD);
- STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
- stb0899_write_reg(state, STB0899_RTF, reg);
-
+#if 1
+ /* TODO: Only for the moment and for TT3200 */
+ if ( ((internal->freq > 1870000) && (internal->freq < 1890000))
+ || ((internal->freq > 1570000) && (internal->freq < 1590000))
+ || ((internal->freq > 1500000) && (internal->freq < 1520000))
+ )
+ {
+ /* do not disable carrier detector */
+ /* for special frequencies (ProSieben, RTL ...) */
+ printk("%s: special for frequency=%d\n",__func__,internal->freq);
+ }
+ else
+#endif
+ {
+ /* disable carrier detector */
+ reg = stb0899_read_reg(state, STB0899_CFD);
+ STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
+ stb0899_write_reg(state, STB0899_RTF, reg);
+ }
stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
}
@@ -1201,7 +1223,6 @@ static u32 stb0899_dvbs2_get_modcod(stru
static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
{
struct stb0899_internal *internal = &state->internal;
-
s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
u32 csm1, csm2, csm3, csm4;
@@ -1348,6 +1369,8 @@ enum stb0899_status stb0899_dvbs2_algo(s
int i = 0;
u32 reg, csm1;
+ s32 retry = 0;
+ do {
if (internal->srate <= 2000000) {
searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */
FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */
@@ -1370,7 +1393,6 @@ enum stb0899_status stb0899_dvbs2_algo(s
searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */
FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
}
-
/* Maintain Stream Merger in reset during acquisition */
reg = stb0899_read_reg(state, STB0899_TSTRES);
STB0899_SETFIELD_VAL(FRESRS, reg, 1);
@@ -1432,10 +1454,10 @@ enum stb0899_status stb0899_dvbs2_algo(s
internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
i++;
}
- }
-
+ }
+
if (internal->status != DVBS2_FEC_LOCK) {
- if (internal->inversion == IQ_SWAP_AUTO) {
+ /*if (internal->inversion == IQ_SWAP_AUTO)*/ { // TODO: Special for TT3200
reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
/* IQ Spectrum Inversion */
@@ -1551,5 +1573,8 @@ enum stb0899_status stb0899_dvbs2_algo(s
STB0899_SETFIELD_VAL(FRESRS, reg, 0);
stb0899_write_reg(state, STB0899_TSTRES, reg);
- return internal->status;
+ }
+ while ( (++retry < 5) && (internal->status != DVBS2_FEC_LOCK) );
+
+ return internal->status;
}
diff -urNp v4l-dvb.org/linux/drivers/media/dvb/frontends/stb0899_drv.c v4l-dvb/linux/drivers/media/dvb/frontends/stb0899_drv.c
--- v4l-dvb.org/linux/drivers/media/dvb/frontends/stb0899_drv.c 2007-02-19 00:26:05.000000000 +0100
+++ v4l-dvb/linux/drivers/media/dvb/frontends/stb0899_drv.c 2007-05-21 20:57:59.000000000 +0200
@@ -31,7 +31,8 @@
#include "stb0899_priv.h"
#include "stb0899_reg.h"
-static unsigned int verbose = 5;
+//static unsigned int verbose = 5;
+static unsigned int verbose = 0;
module_param(verbose, int, 0644);
/* C/N in dB/10, NIRM/NIRL */
@@ -2013,6 +2014,7 @@ struct dvb_frontend *stb0899_attach(stru
state->i2c = i2c;
state->frontend.ops = stb0899_ops;
state->frontend.demodulator_priv = state;
+ state->delsys = DVBFE_DELSYS_DVBS;
stb0899_wakeup(&state->frontend);
if (stb0899_get_dev_id(state) == -ENODEV) {
diff -urNp v4l-dvb.org/linux/drivers/media/dvb/frontends/stb6100.c v4l-dvb/linux/drivers/media/dvb/frontends/stb6100.c
--- v4l-dvb.org/linux/drivers/media/dvb/frontends/stb6100.c 2007-02-10 17:37:22.000000000 +0100
+++ v4l-dvb/linux/drivers/media/dvb/frontends/stb6100.c 2007-05-21 21:00:12.000000000 +0200
@@ -27,10 +27,10 @@
#include "dvb_frontend.h"
#include "stb6100.h"
-static unsigned int verbose;
+//static unsigned int verbose;
+static unsigned int verbose = 0;
module_param(verbose, int, 0644);
-
#define FE_ERROR 0
#define FE_NOTICE 1
#define FE_INFO 2
@@ -423,6 +423,20 @@ static int stb6100_set_frequency(struct
if ((rc = stb6100_write_reg(state, STB6100_VCO, regs[STB6100_VCO])) < 0)
return rc;
+///XXX
+ {
+ int rc;
+ unsigned long start = jiffies;
+
+ while ((rc = stb6100_read_reg(state, STB6100_LD)) >=0) {
+ if (rc & STB6100_LD_LOCK)
+ break;
+ if (jiffies - start > 100)
+ break;
+ msleep(10);
+ }
+ }
+
msleep(5); /* wait for LO to lock */
regs[STB6100_VCO] &= ~STB6100_VCO_OSCH; /* vco search disabled */
regs[STB6100_VCO] |= STB6100_VCO_OCK; /* search clock off */
@@ -445,6 +459,8 @@ static int stb6100_init(struct dvb_front
{
struct stb6100_state *state = fe->tuner_priv;
struct tuner_state *status = &state->status;
+
+ printk("%s:\n",__func__);
status->tunerstep = 125000;
status->ifreq = 0;
@@ -545,7 +561,7 @@ struct dvb_frontend *stb6100_attach(stru
fe->tuner_priv = state;
fe->ops.tuner_ops = stb6100_ops;
- printk("%s: Attaching\n", __func__);
+ printk("%s: Attaching STB6100\n", __func__);
return fe;
error:
diff -urNp v4l-dvb.org/linux/drivers/media/dvb/ttpci/budget-ci.c v4l-dvb/linux/drivers/media/dvb/ttpci/budget-ci.c
--- v4l-dvb.org/linux/drivers/media/dvb/ttpci/budget-ci.c 2007-02-22 14:20:08.000000000 +0100
+++ v4l-dvb/linux/drivers/media/dvb/ttpci/budget-ci.c 2007-05-21 19:16:42.000000000 +0200
@@ -47,6 +47,10 @@
#include "bsbe1.h"
#include "bsru6.h"
+#include "stb0899_drv.h"
+#include "stb0899_reg.h"
+#include "stb6100.h"
+
/*
* Regarding DEBIADDR_IR:
* Some CI modules hang if random addresses are read.
@@ -1084,7 +1088,851 @@ static struct stv0297_config dvbc_philip
.stop_during_read = 1,
};
+/* TT S2-3200 DVB-S (STB0899) Inittab */
+static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = {
+#if 1
+// 0x0000000b , /* SYSREG */
+ { STB0899_DEV_ID , 0x81 },
+ { STB0899_DISCNTRL1 , 0x32 },
+ { STB0899_DISCNTRL2 , 0x80 },
+ { STB0899_DISRX_ST0 , 0x04 },
+ { STB0899_DISRX_ST1 , 0x00 },
+ { STB0899_DISPARITY , 0x00 },
+ { STB0899_DISFIFO , 0x00 },
+ { STB0899_DISSTATUS , 0x20 },
+ { STB0899_DISF22 , 0x8c },
+ { STB0899_DISF22RX , 0x9a },
+ //SYSREG ?
+ { STB0899_ACRPRESC , 0x11 },
+ { STB0899_ACRDIV1 , 0x0a },
+ { STB0899_ACRDIV2 , 0x05 },
+ { STB0899_DACR1 , 0x00 },
+ { STB0899_DACR2 , 0x00 },
+ { STB0899_OUTCFG , 0x00 },
+ { STB0899_MODECFG , 0x00 },
+ { STB0899_IRQSTATUS_3 , 0x30 },
+ { STB0899_IRQSTATUS_2 , 0x00 },
+ { STB0899_IRQSTATUS_1 , 0x00 },
+ { STB0899_IRQSTATUS_0 , 0x00 },
+ { STB0899_IRQMSK_3 , 0xf3 },
+ { STB0899_IRQMSK_2 , 0xfc },
+ { STB0899_IRQMSK_1 , 0xff },
+ { STB0899_IRQMSK_0 , 0xff },
+ { STB0899_IRQCFG , 0x00 },
+ { STB0899_I2CCFG , 0x88 },
+ { STB0899_I2CRPT , 0x5c },
+ { STB0899_IOPVALUE5 , 0x00 },
+ { STB0899_IOPVALUE4 , 0x20 },
+ { STB0899_IOPVALUE3 , 0xc9 },
+ { STB0899_IOPVALUE2 , 0x90 },
+ { STB0899_IOPVALUE1 , 0x40 },
+ { STB0899_IOPVALUE0 , 0x00 },
+ { STB0899_GPIO00CFG , 0x82 },
+ { STB0899_GPIO01CFG , 0x82 },
+ { STB0899_GPIO02CFG , 0x82 },
+ { STB0899_GPIO03CFG , 0x82 },
+ { STB0899_GPIO04CFG , 0x82 },
+ { STB0899_GPIO05CFG , 0x82 },
+ { STB0899_GPIO06CFG , 0x82 },
+ { STB0899_GPIO07CFG , 0x82 },
+ { STB0899_GPIO08CFG , 0x82 },
+ { STB0899_GPIO09CFG , 0x82 },
+ { STB0899_GPIO10CFG , 0x82 },
+ { STB0899_GPIO11CFG , 0x82 },
+ { STB0899_GPIO12CFG , 0x82 },
+ { STB0899_GPIO13CFG , 0x82 },
+ { STB0899_GPIO14CFG , 0x82 },
+ { STB0899_GPIO15CFG , 0x82 },
+ { STB0899_GPIO16CFG , 0x82 },
+ { STB0899_GPIO17CFG , 0x82 },
+ { STB0899_GPIO18CFG , 0x82 },
+ { STB0899_GPIO19CFG , 0x82 },
+ { STB0899_GPIO20CFG , 0x82 },
+ { STB0899_SDATCFG , 0xb8 },
+ { STB0899_SCLTCFG , 0xba },
+ { STB0899_AGCRFCFG , 0x1c }, // 0x11
+ { STB0899_GPIO22 , 0x82 }, // AGCBB2CFG
+ { STB0899_GPIO21 , 0x91 }, // AGCBB1CFG
+ { STB0899_DIRCLKCFG , 0x82 },
+ { STB0899_CLKOUT27CFG , 0x7e },
+ { STB0899_STDBYCFG , 0x82 },
+ { STB0899_CS0CFG , 0x82 },
+ { STB0899_CS1CFG , 0x82 },
+ { STB0899_DISEQCOCFG , 0x20 },
+ { STB0899_GPIO32CFG , 0x82 },
+ { STB0899_GPIO33CFG , 0x82 },
+ { STB0899_GPIO34CFG , 0x82 },
+ { STB0899_GPIO35CFG , 0x82 },
+ { STB0899_GPIO36CFG , 0x82 },
+ { STB0899_GPIO37CFG , 0x82 },
+ { STB0899_GPIO38CFG , 0x82 },
+ { STB0899_GPIO39CFG , 0x82 },
+ { STB0899_NCOARSE , 0x15 }, // 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz
+ { STB0899_SYNTCTRL , 0x02 }, // 0x00 = CLK from CLKI, 0x02 = CLK from XTALI
+ { STB0899_FILTCTRL , 0x00 },
+ { STB0899_SYSCTRL , 0x00 },
+ { STB0899_STOPCLK1 , 0x20 },
+ { STB0899_STOPCLK2 , 0x00 },
+ { STB0899_INTBUFSTATUS , 0x00 },
+ { STB0899_INTBUFCTRL , 0x0a },
+ { 0xffff , 0xff },
+#else
+// 0x0000000b , /* SYSREG */
+ { STB0899_DEV_ID , 0x30 /*0x81*/ }, //
+ { STB0899_DISCNTRL1 , 0x32 },
+ { STB0899_DISCNTRL2 , 0x80 },
+ { STB0899_DISRX_ST0 , 0x04 },
+ { STB0899_DISRX_ST1 , 0x00 },
+ { STB0899_DISPARITY , 0x00 },
+ { STB0899_DISFIFO , 0x00 },
+ { STB0899_DISSTATUS , 0x20 },
+ { STB0899_DISF22 , 0x8c },
+ { STB0899_DISF22RX , 0x9a },
+ { STB0899_SYSREG , 0x0B }, //
+ //SYSREG ?
+ { STB0899_ACRPRESC , 0x11 },
+ { STB0899_ACRDIV1 , 0x0a },
+ { STB0899_ACRDIV2 , 0x05 },
+ { STB0899_DACR1 , 0x00 },
+ { STB0899_DACR2 , 0x00 },
+ { STB0899_OUTCFG , 0x00 },
+ { STB0899_MODECFG , 0x00 },
+ { STB0899_IRQSTATUS_3 , 0xFE /*0x30*/ },
+ { STB0899_IRQSTATUS_2 , 0x80 /*0x00*/ },
+ { STB0899_IRQSTATUS_1 , 0xBC /*0x00*/ },
+ { STB0899_IRQSTATUS_0 , 0xF4 /*0x00*/ },
+ { STB0899_IRQMSK_3 , 0xf3 },
+ { STB0899_IRQMSK_2 , 0xfc },
+ { STB0899_IRQMSK_1 , 0xff },
+ { STB0899_IRQMSK_0 , 0xff },
+ { STB0899_IRQCFG , 0x00 },
+ { STB0899_I2CCFG , 0x88 },
+ { STB0899_I2CRPT , 0x5c },
+ { STB0899_IOPVALUE5 , 0x00 },
+ { STB0899_IOPVALUE4 , 0x33 /*0x20*/ },
+ { STB0899_IOPVALUE3 , 0x51 /*0xc9*/ },
+ { STB0899_IOPVALUE2 , 0x90 },
+ { STB0899_IOPVALUE1 , 0x40 },
+ { STB0899_IOPVALUE0 , 0x00 },
+ { STB0899_GPIO00CFG , 0x82 },
+ { STB0899_GPIO01CFG , 0x82 },
+ { STB0899_GPIO02CFG , 0x82 },
+ { STB0899_GPIO03CFG , 0x82 },
+ { STB0899_GPIO04CFG , 0x82 },
+ { STB0899_GPIO05CFG , 0x82 },
+ { STB0899_GPIO06CFG , 0x82 },
+ { STB0899_GPIO07CFG , 0x82 },
+ { STB0899_GPIO08CFG , 0x82 },
+ { STB0899_GPIO09CFG , 0x82 },
+ { STB0899_GPIO10CFG , 0x82 },
+ { STB0899_GPIO11CFG , 0x82 },
+ { STB0899_GPIO12CFG , 0x82 },
+ { STB0899_GPIO13CFG , 0x82 },
+ { STB0899_GPIO14CFG , 0x82 },
+ { STB0899_GPIO15CFG , 0x82 },
+ { STB0899_GPIO16CFG , 0x82 },
+ { STB0899_GPIO17CFG , 0x82 },
+ { STB0899_GPIO18CFG , 0x82 },
+ { STB0899_GPIO19CFG , 0x82 },
+ { STB0899_GPIO20CFG , 0x82 },
+ { STB0899_SDATCFG , 0xb8 },
+ { STB0899_SCLTCFG , 0xba },
+ { STB0899_AGCRFCFG , 0x1c }, // 0x11
+ { STB0899_GPIO22 , 0x82 }, // AGCBB2CFG
+ { STB0899_GPIO21 , 0x91 }, // AGCBB1CFG
+ { STB0899_DIRCLKCFG , 0x82 },
+ { STB0899_CLKOUT27CFG , 0x7e },
+ { STB0899_STDBYCFG , 0x82 },
+ { STB0899_CS0CFG , 0x82 },
+ { STB0899_CS1CFG , 0x82 },
+ { STB0899_DISEQCOCFG , 0x20 },
+ { STB0899_GPIO32CFG , 0x82 },
+ { STB0899_GPIO33CFG , 0x82 },
+ { STB0899_GPIO34CFG , 0x82 },
+ { STB0899_GPIO35CFG , 0x82 },
+ { STB0899_GPIO36CFG , 0x82 },
+ { STB0899_GPIO37CFG , 0x82 },
+ { STB0899_GPIO38CFG , 0x82 },
+ { STB0899_GPIO39CFG , 0x82 },
+ { STB0899_NCOARSE , 0x17 /*0x15*/ }, // 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz
+ { STB0899_SYNTCTRL , 0x02 }, // 0x00 = CLK from CLKI, 0x02 = CLK from XTALI
+ { STB0899_FILTCTRL , 0x00 },
+ { STB0899_SYSCTRL , 0x00 },
+ { STB0899_STOPCLK1 , 0x20 },
+ { STB0899_STOPCLK2 , 0x00 },
+ { STB0899_INTBUFSTATUS , 0x00 },
+ { STB0899_INTBUFCTRL , 0x0a },
+ { 0xffff , 0xff },
+#endif
+};
+
+static const struct stb0899_s2_reg tt3200_stb0899_s2_init_2[] = {
+
+ { STB0899_OFF0_DMD_STATUS , STB0899_BASE_DMD_STATUS , 0x00000103 }, /* DMDSTATUS */
+ { STB0899_OFF0_CRL_FREQ , STB0899_BASE_CRL_FREQ , 0x3ed1da56 }, /* CRLFREQ */
+ { STB0899_OFF0_BTR_FREQ , STB0899_BASE_BTR_FREQ , 0x00004000 }, /* BTRFREQ */
+ { STB0899_OFF0_IF_AGC_GAIN , STB0899_BASE_IF_AGC_GAIN , 0x00002ade }, /* IFAGCGAIN */
+ { STB0899_OFF0_BB_AGC_GAIN , STB0899_BASE_BB_AGC_GAIN , 0x000001bc }, /* BBAGCGAIN */
+ { STB0899_OFF0_DC_OFFSET , STB0899_BASE_DC_OFFSET , 0x00000200 }, /* DCOFFSET */
+ { STB0899_OFF0_DMD_CNTRL , STB0899_BASE_DMD_CNTRL , 0x0000000f }, /* DMDCNTRL */
+
+ { STB0899_OFF0_IF_AGC_CNTRL , STB0899_BASE_IF_AGC_CNTRL , 0x03fb4a20 }, /* IFAGCCNTRL */
+ { STB0899_OFF0_BB_AGC_CNTRL , STB0899_BASE_BB_AGC_CNTRL , 0x00200c97 }, /* BBAGCCNTRL */
+
+ { STB0899_OFF0_CRL_CNTRL , STB0899_BASE_CRL_CNTRL , 0x00000016 }, /* CRLCNTRL */
+ { STB0899_OFF0_CRL_PHS_INIT , STB0899_BASE_CRL_PHS_INIT , 0x00000000 }, /* CRLPHSINIT */
+ { STB0899_OFF0_CRL_FREQ_INIT , STB0899_BASE_CRL_FREQ_INIT , 0x00000000 }, /* CRLFREQINIT */
+ { STB0899_OFF0_CRL_LOOP_GAIN , STB0899_BASE_CRL_LOOP_GAIN , 0x00000000 }, /* CRLLOOPGAIN */
+ { STB0899_OFF0_CRL_NOM_FREQ , STB0899_BASE_CRL_NOM_FREQ , 0x3ed097b6 }, /* CRLNOMFREQ */
+ { STB0899_OFF0_CRL_SWP_RATE , STB0899_BASE_CRL_SWP_RATE , 0x00000000 }, /* CRLSWPRATE */
+ { STB0899_OFF0_CRL_MAX_SWP , STB0899_BASE_CRL_MAX_SWP , 0x00000000 }, /* CRLMAXSWP */
+ { STB0899_OFF0_CRL_LK_CNTRL , STB0899_BASE_CRL_LK_CNTRL , 0x0f6cdc01 }, /* CRLLKCNTRL */
+ { STB0899_OFF0_DECIM_CNTRL , STB0899_BASE_DECIM_CNTRL , 0x00000000 }, /* DECIMCNTRL */
+ { STB0899_OFF0_BTR_CNTRL , STB0899_BASE_BTR_CNTRL , 0x00003993 }, /* BTRCNTRL */
+ { STB0899_OFF0_BTR_LOOP_GAIN , STB0899_BASE_BTR_LOOP_GAIN , 0x000d3c6f }, /* BTRLOOPGAIN */
+ { STB0899_OFF0_BTR_PHS_INIT , STB0899_BASE_BTR_PHS_INIT , 0x00000000 }, /* BTRPHSINIT */
+ { STB0899_OFF0_BTR_FREQ_INIT , STB0899_BASE_BTR_FREQ_INIT , 0x00000000 }, /* BTRFREQINIT */
+ { STB0899_OFF0_BTR_NOM_FREQ , STB0899_BASE_BTR_NOM_FREQ , 0x0238e38e }, /* BTRNOMFREQ */
+ { STB0899_OFF0_BTR_LK_CNTRL , STB0899_BASE_BTR_LK_CNTRL , 0x00000000 }, /* BTRLKCNTRL */
+ { STB0899_OFF0_DECN_CNTRL , STB0899_BASE_DECN_CNTRL , 0x00000000 }, /* DECNCNTRL */
+ { STB0899_OFF0_TP_CNTRL , STB0899_BASE_TP_CNTRL , 0x00000000 }, /* TPCNTRL */
+ { STB0899_OFF0_TP_BUF_STATUS , STB0899_BASE_TP_BUF_STATUS , 0x00000000 }, /* TPBUFSTATUS */
+ { STB0899_OFF0_DC_ESTIM , STB0899_BASE_DC_ESTIM , 0x00000000 }, /* DCESTIM */
+ { STB0899_OFF0_FLL_CNTRL , STB0899_BASE_FLL_CNTRL , 0x00000000 }, /* FLLCNTRL */
+ { STB0899_OFF0_FLL_FREQ_WD , STB0899_BASE_FLL_FREQ_WD , 0x40070000 }, /* FLLFREQWD */
+ { STB0899_OFF0_ANTI_ALIAS_SEL , STB0899_BASE_ANTI_ALIAS_SEL , 0x00000001 }, /* ANTIALIASSEL */
+ { STB0899_OFF0_RRC_ALPHA , STB0899_BASE_RRC_ALPHA , 0x00000002 }, /* RRCALPHA */
+ { STB0899_OFF0_DC_ADAPT_LSHFT , STB0899_BASE_DC_ADAPT_LSHFT , 0x00000000 }, /* DCADAPTISHFT */
+ { STB0899_OFF0_IMB_OFFSET , STB0899_BASE_IMB_OFFSET , 0x0000fe01 }, /* IMBOFFSET */
+ { STB0899_OFF0_IMB_ESTIMATE , STB0899_BASE_IMB_ESTIMATE , 0x00000000 }, /* IMBESTIMATE */
+ { STB0899_OFF0_IMB_CNTRL , STB0899_BASE_IMB_CNTRL , 0x00000001 }, /* IMBCNTRL */
+ { STB0899_OFF0_IF_AGC_CNTRL2 , STB0899_BASE_IF_AGC_CNTRL2 , 0x00005007 }, /* IFAGCCNTRL2 */
+ { STB0899_OFF0_DMD_CNTRL2 , STB0899_BASE_DMD_CNTRL2 , 0x00000002 }, /* DMDCNTRL2 */
+ { STB0899_OFF0_TP_BUFFER , STB0899_BASE_TP_BUFFER , 0x00000000 }, /* TPBUFFER */
+ { STB0899_OFF0_TP_BUFFER1 , STB0899_BASE_TP_BUFFER1 , 0x00000000 }, /* TPBUFFER1 */
+ { STB0899_OFF0_TP_BUFFER2 , STB0899_BASE_TP_BUFFER2 , 0x00000000 }, /* TPBUFFER2 */
+ { STB0899_OFF0_TP_BUFFER3 , STB0899_BASE_TP_BUFFER3 , 0x00000000 }, /* TPBUFFER3 */
+ { STB0899_OFF0_TP_BUFFER4 , STB0899_BASE_TP_BUFFER4 , 0x00000000 }, /* TPBUFFER4 */
+ { STB0899_OFF0_TP_BUFFER5 , STB0899_BASE_TP_BUFFER5 , 0x00000000 }, /* TPBUFFER5 */
+ { STB0899_OFF0_TP_BUFFER6 , STB0899_BASE_TP_BUFFER6 , 0x00000000 }, /* TPBUFFER6 */
+ { STB0899_OFF0_TP_BUFFER7 , STB0899_BASE_TP_BUFFER7 , 0x00000000 }, /* TPBUFFER7 */
+ { STB0899_OFF0_TP_BUFFER8 , STB0899_BASE_TP_BUFFER8 , 0x00000000 }, /* TPBUFFER8 */
+ { STB0899_OFF0_TP_BUFFER9 , STB0899_BASE_TP_BUFFER9 , 0x00000000 }, /* TPBUFFER9 */
+ { STB0899_OFF0_TP_BUFFER10 , STB0899_BASE_TP_BUFFER10 , 0x00000000 }, /* TPBUFFER10 */
+ { STB0899_OFF0_TP_BUFFER11 , STB0899_BASE_TP_BUFFER11 , 0x00000000 }, /* TPBUFFER11 */
+ { STB0899_OFF0_TP_BUFFER12 , STB0899_BASE_TP_BUFFER12 , 0x00000000 }, /* TPBUFFER12 */
+ { STB0899_OFF0_TP_BUFFER13 , STB0899_BASE_TP_BUFFER13 , 0x00000000 }, /* TPBUFFER13 */
+ { STB0899_OFF0_TP_BUFFER14 , STB0899_BASE_TP_BUFFER14 , 0x00000000 }, /* TPBUFFER14 */
+ { STB0899_OFF0_TP_BUFFER15 , STB0899_BASE_TP_BUFFER15 , 0x00000000 }, /* TPBUFFER15 */
+ { STB0899_OFF0_TP_BUFFER16 , STB0899_BASE_TP_BUFFER16 , 0x0000ff00 }, /* TPBUFFER16 */
+ { STB0899_OFF0_TP_BUFFER17 , STB0899_BASE_TP_BUFFER17 , 0x00000100 }, /* TPBUFFER17 */
+ { STB0899_OFF0_TP_BUFFER18 , STB0899_BASE_TP_BUFFER18 , 0x0000fe01 }, /* TPBUFFER18 */
+ { STB0899_OFF0_TP_BUFFER19 , STB0899_BASE_TP_BUFFER19 , 0x000004fe }, /* TPBUFFER19 */
+ { STB0899_OFF0_TP_BUFFER20 , STB0899_BASE_TP_BUFFER20 , 0x0000cfe7 }, /* TPBUFFER20 */
+ { STB0899_OFF0_TP_BUFFER21 , STB0899_BASE_TP_BUFFER21 , 0x0000bec6 }, /* TPBUFFER21 */
+ { STB0899_OFF0_TP_BUFFER22 , STB0899_BASE_TP_BUFFER22 , 0x0000c2bf }, /* TPBUFFER22 */
+ { STB0899_OFF0_TP_BUFFER23 , STB0899_BASE_TP_BUFFER23 , 0x0000c1c1 }, /* TPBUFFER23 */
+ { STB0899_OFF0_TP_BUFFER24 , STB0899_BASE_TP_BUFFER24 , 0x0000c1c1 }, /* TPBUFFER24 */
+ { STB0899_OFF0_TP_BUFFER25 , STB0899_BASE_TP_BUFFER25 , 0x0000c1c1 }, /* TPBUFFER25 */
+ { STB0899_OFF0_TP_BUFFER26 , STB0899_BASE_TP_BUFFER26 , 0x0000c1c1 }, /* TPBUFFER26 */
+ { STB0899_OFF0_TP_BUFFER27 , STB0899_BASE_TP_BUFFER27 , 0x0000c1c0 }, /* TPBUFFER27 */
+ { STB0899_OFF0_TP_BUFFER28 , STB0899_BASE_TP_BUFFER28 , 0x0000c0c0 }, /* TPBUFFER28 */
+ { STB0899_OFF0_TP_BUFFER29 , STB0899_BASE_TP_BUFFER29 , 0x0000c1c1 }, /* TPBUFFER29 */
+ { STB0899_OFF0_TP_BUFFER30 , STB0899_BASE_TP_BUFFER30 , 0x0000c1c1 }, /* TPBUFFER30 */
+ { STB0899_OFF0_TP_BUFFER31 , STB0899_BASE_TP_BUFFER31 , 0x0000c0c1 }, /* TPBUFFER31 */
+ { STB0899_OFF0_TP_BUFFER32 , STB0899_BASE_TP_BUFFER32 , 0x0000c0c1 }, /* TPBUFFER32 */
+ { STB0899_OFF0_TP_BUFFER33 , STB0899_BASE_TP_BUFFER33 , 0x0000c1c1 }, /* TPBUFFER33 */
+ { STB0899_OFF0_TP_BUFFER34 , STB0899_BASE_TP_BUFFER34 , 0x0000c1c1 }, /* TPBUFFER34 */
+ { STB0899_OFF0_TP_BUFFER35 , STB0899_BASE_TP_BUFFER35 , 0x0000c0c1 }, /* TPBUFFER35 */
+ { STB0899_OFF0_TP_BUFFER36 , STB0899_BASE_TP_BUFFER36 , 0x0000c1c1 }, /* TPBUFFER36 */
+ { STB0899_OFF0_TP_BUFFER37 , STB0899_BASE_TP_BUFFER37 , 0x0000c0c1 }, /* TPBUFFER37 */
+ { STB0899_OFF0_TP_BUFFER38 , STB0899_BASE_TP_BUFFER38 , 0x0000c1c1 }, /* TPBUFFER38 */
+ { STB0899_OFF0_TP_BUFFER39 , STB0899_BASE_TP_BUFFER39 , 0x0000c0c0 }, /* TPBUFFER39 */
+ { STB0899_OFF0_TP_BUFFER40 , STB0899_BASE_TP_BUFFER40 , 0x0000c1c0 }, /* TPBUFFER40 */
+ { STB0899_OFF0_TP_BUFFER41 , STB0899_BASE_TP_BUFFER41 , 0x0000c1c1 }, /* TPBUFFER41 */
+ { STB0899_OFF0_TP_BUFFER42 , STB0899_BASE_TP_BUFFER42 , 0x0000c0c0 }, /* TPBUFFER42 */
+ { STB0899_OFF0_TP_BUFFER43 , STB0899_BASE_TP_BUFFER43 , 0x0000c1c0 }, /* TPBUFFER43 */
+ { STB0899_OFF0_TP_BUFFER44 , STB0899_BASE_TP_BUFFER44 , 0x0000c0c1 }, /* TPBUFFER44 */
+ { STB0899_OFF0_TP_BUFFER45 , STB0899_BASE_TP_BUFFER45 , 0x0000c1be }, /* TPBUFFER45 */
+ { STB0899_OFF0_TP_BUFFER46 , STB0899_BASE_TP_BUFFER46 , 0x0000c1c9 }, /* TPBUFFER46 */
+ { STB0899_OFF0_TP_BUFFER47 , STB0899_BASE_TP_BUFFER47 , 0x0000c0da }, /* TPBUFFER47 */
+ { STB0899_OFF0_TP_BUFFER48 , STB0899_BASE_TP_BUFFER48 , 0x0000c0ba }, /* TPBUFFER48 */
+ { STB0899_OFF0_TP_BUFFER49 , STB0899_BASE_TP_BUFFER49 , 0x0000c1c4 }, /* TPBUFFER49 */
+ { STB0899_OFF0_TP_BUFFER50 , STB0899_BASE_TP_BUFFER50 , 0x0000c1bf }, /* TPBUFFER50 */
+ { STB0899_OFF0_TP_BUFFER51 , STB0899_BASE_TP_BUFFER51 , 0x0000c0c1 }, /* TPBUFFER51 */
+ { STB0899_OFF0_TP_BUFFER52 , STB0899_BASE_TP_BUFFER52 , 0x0000c1c0 }, /* TPBUFFER52 */
+ { STB0899_OFF0_TP_BUFFER53 , STB0899_BASE_TP_BUFFER53 , 0x0000c0c1 }, /* TPBUFFER53 */
+ { STB0899_OFF0_TP_BUFFER54 , STB0899_BASE_TP_BUFFER54 , 0x0000c1c1 }, /* TPBUFFER54 */
+ { STB0899_OFF0_TP_BUFFER55 , STB0899_BASE_TP_BUFFER55 , 0x0000c1c1 }, /* TPBUFFER55 */
+ { STB0899_OFF0_TP_BUFFER56 , STB0899_BASE_TP_BUFFER56 , 0x0000c1c1 }, /* TPBUFFER56 */
+ { STB0899_OFF0_TP_BUFFER57 , STB0899_BASE_TP_BUFFER57 , 0x0000c1c1 }, /* TPBUFFER57 */
+ { STB0899_OFF0_TP_BUFFER58 , STB0899_BASE_TP_BUFFER58 , 0x0000c1c1 }, /* TPBUFFER58 */
+ { STB0899_OFF0_TP_BUFFER59 , STB0899_BASE_TP_BUFFER59 , 0x0000c1c1 }, /* TPBUFFER59 */
+ { STB0899_OFF0_TP_BUFFER60 , STB0899_BASE_TP_BUFFER60 , 0x0000c1c1 }, /* TPBUFFER60 */
+ { STB0899_OFF0_TP_BUFFER61 , STB0899_BASE_TP_BUFFER61 , 0x0000c1c1 }, /* TPBUFFER61 */
+ { STB0899_OFF0_TP_BUFFER62 , STB0899_BASE_TP_BUFFER62 , 0x0000c1c1 }, /* TPBUFFER62 */
+ { STB0899_OFF0_TP_BUFFER63 , STB0899_BASE_TP_BUFFER63 , 0x0000c1c0 }, /* TPBUFFER63 */
+ { STB0899_OFF0_RESET_CNTRL , STB0899_BASE_RESET_CNTRL , 0x00000001 }, /* RESETCNTRL */
+ { STB0899_OFF0_ACM_ENABLE , STB0899_BASE_ACM_ENABLE , 0x00005654 }, /* ACMENABLE */
+ { STB0899_OFF0_DESCR_CNTRL , STB0899_BASE_DESCR_CNTRL , 0x00000000 }, /* DESCRCNTRL */
+ { STB0899_OFF0_CSM_CNTRL1 , STB0899_BASE_CSM_CNTRL1 , 0x00020019 }, /* CSMCNTRL1 */
+ { STB0899_OFF0_CSM_CNTRL2 , STB0899_BASE_CSM_CNTRL2 , 0x004b3237 }, /* CSMCNTRL2 */
+ { STB0899_OFF0_CSM_CNTRL3 , STB0899_BASE_CSM_CNTRL3 , 0x0003dd17 }, /* CSMCNTRL3 */
+ { STB0899_OFF0_CSM_CNTRL4 , STB0899_BASE_CSM_CNTRL4 , 0x00008008 }, /* CSMCNTRL4 */
+ { STB0899_OFF0_UWP_CNTRL1 , STB0899_BASE_UWP_CNTRL1 , 0x002a3106 }, /* UWPCNTRL1 */
+ { STB0899_OFF0_UWP_CNTRL2 , STB0899_BASE_UWP_CNTRL2 , 0x0006140a }, /* UWPCNTRL2 */
+ { STB0899_OFF0_UWP_STAT1 , STB0899_BASE_UWP_STAT1 , 0x00008000 }, /* UWPSTAT1 */
+ { STB0899_OFF0_UWP_STAT2 , STB0899_BASE_UWP_STAT2 , 0x00000000 }, /* UWPSTAT2 */
+ { STB0899_OFF0_DMD_STAT2 , STB0899_BASE_DMD_STAT2 , 0x00000000 }, /* DMDSTAT2 */
+ { STB0899_OFF0_FREQ_ADJ_SCALE , STB0899_BASE_FREQ_ADJ_SCALE , 0x00000471 }, /* FREQADJSCALE */
+ { STB0899_OFF0_UWP_CNTRL3 , STB0899_BASE_UWP_CNTRL3 , 0x017b0465 }, /* UWPCNTRL3 */
+ { STB0899_OFF0_SYM_CLK_SEL , STB0899_BASE_SYM_CLK_SEL , 0x00000002 }, /* SYMCLKSEL */
+ { STB0899_OFF0_SOF_SRCH_TO , STB0899_BASE_SOF_SRCH_TO , 0x00196464 }, /* SOFSRCHTO */
+ { STB0899_OFF0_ACQ_CNTRL1 , STB0899_BASE_ACQ_CNTRL1 , 0x00000603 }, /* ACQCNTRL1 */
+ { STB0899_OFF0_ACQ_CNTRL2 , STB0899_BASE_ACQ_CNTRL2 , 0x02046666 }, /* ACQCNTRL2 */
+ { STB0899_OFF0_ACQ_CNTRL3 , STB0899_BASE_ACQ_CNTRL3 , 0x10046583 }, /* ACQCNTRL3 */
+ { STB0899_OFF0_FE_SETTLE , STB0899_BASE_FE_SETTLE , 0x00010404 }, /* FESETTLE */
+ { STB0899_OFF0_AC_DWELL , STB0899_BASE_AC_DWELL , 0x0002aa8a }, /* ACDWELL */
+ { STB0899_OFF0_ACQUIRE_TRIG , STB0899_BASE_ACQUIRE_TRIG , 0x00000000 }, /* ACQUIRETRIG */
+ { STB0899_OFF0_LOCK_LOST , STB0899_BASE_LOCK_LOST , 0x00000001 }, /* LOCKLOST */
+ { STB0899_OFF0_ACQ_STAT1 , STB0899_BASE_ACQ_STAT1 , 0x00000500 }, /* ACQSTAT1 */
+ { STB0899_OFF0_ACQ_TIMEOUT , STB0899_BASE_ACQ_TIMEOUT , 0x0028a0a0 }, /* ACQTIMEOUT */
+ { STB0899_OFF0_ACQ_TIME , STB0899_BASE_ACQ_TIME , 0x00000000 }, /* ACQTIME */
+ { STB0899_OFF0_FINAL_AGC_CNTRL , STB0899_BASE_FINAL_AGC_CNTRL , 0x00800c17 }, /* FINALAGCCNTRL*/
+ { STB0899_OFF0_FINAL_AGC_GAIN , STB0899_BASE_FINAL_AGC_GAIN , 0x00000000 }, /* FINALAGCCGAIN*/
+ { STB0899_OFF0_EQUALIZER_INIT , STB0899_BASE_EQUALIZER_INIT , 0x00000000 }, /* EQUILIZERINIT*/
+ { STB0899_OFF0_EQ_CNTRL , STB0899_BASE_EQ_CNTRL , 0x00054802 }, /* EQCNTL */
+ { STB0899_OFF0_EQ_I_INIT_COEFF_0, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF0 */
+ { STB0899_OFF1_EQ_I_INIT_COEFF_1, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF1 */
+ { STB0899_OFF2_EQ_I_INIT_COEFF_2, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF2 */
+ { STB0899_OFF3_EQ_I_INIT_COEFF_3, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF3 */
+ { STB0899_OFF4_EQ_I_INIT_COEFF_4, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF4 */
+ { STB0899_OFF5_EQ_I_INIT_COEFF_5, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000400 }, /* EQIINITCOEFF5 */
+ { STB0899_OFF6_EQ_I_INIT_COEFF_6, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF6 */
+ { STB0899_OFF7_EQ_I_INIT_COEFF_7, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF7 */
+ { STB0899_OFF8_EQ_I_INIT_COEFF_8, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF8 */
+ { STB0899_OFF9_EQ_I_INIT_COEFF_9, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF9 */
+ { STB0899_OFFa_EQ_I_INIT_COEFF_10,STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF10*/
+ { STB0899_OFF0_EQ_Q_INIT_COEFF_0, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF0 */
+ { STB0899_OFF1_EQ_Q_INIT_COEFF_1, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF1 */
+ { STB0899_OFF2_EQ_Q_INIT_COEFF_2, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF2 */
+ { STB0899_OFF3_EQ_Q_INIT_COEFF_3, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF3 */
+ { STB0899_OFF4_EQ_Q_INIT_COEFF_4, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF4 */
+ { STB0899_OFF5_EQ_Q_INIT_COEFF_5, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF5 */
+ { STB0899_OFF6_EQ_Q_INIT_COEFF_6, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF6 */
+ { STB0899_OFF7_EQ_Q_INIT_COEFF_7, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF7 */
+ { STB0899_OFF8_EQ_Q_INIT_COEFF_8, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF8 */
+ { STB0899_OFF9_EQ_Q_INIT_COEFF_9, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF9 */
+ { STB0899_OFFa_EQ_Q_INIT_COEFF_10,STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF10*/
+ { STB0899_OFF0_EQ_I_OUT_COEFF_0 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT0 */
+ { STB0899_OFF1_EQ_I_OUT_COEFF_1 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT1 */
+ { STB0899_OFF2_EQ_I_OUT_COEFF_2 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT2 */
+ { STB0899_OFF3_EQ_I_OUT_COEFF_3 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT3 */
+ { STB0899_OFF4_EQ_I_OUT_COEFF_4 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT4 */
+ { STB0899_OFF5_EQ_I_OUT_COEFF_5 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT5 */
+ { STB0899_OFF6_EQ_I_OUT_COEFF_6 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT6 */
+ { STB0899_OFF7_EQ_I_OUT_COEFF_7 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT7 */
+ { STB0899_OFF8_EQ_I_OUT_COEFF_8 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT8 */
+ { STB0899_OFF9_EQ_I_OUT_COEFF_9 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT9 */
+ { STB0899_OFFa_EQ_I_OUT_COEFF_10,STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT10*/
+ { STB0899_OFF0_EQ_Q_OUT_COEFF_0 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT0 */
+ { STB0899_OFF1_EQ_Q_OUT_COEFF_1 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT1 */
+ { STB0899_OFF2_EQ_Q_OUT_COEFF_2 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT2 */
+ { STB0899_OFF3_EQ_Q_OUT_COEFF_3 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT3 */
+ { STB0899_OFF4_EQ_Q_OUT_COEFF_4 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT4 */
+ { STB0899_OFF5_EQ_Q_OUT_COEFF_5 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT5 */
+ { STB0899_OFF6_EQ_Q_OUT_COEFF_6 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT6 */
+ { STB0899_OFF7_EQ_Q_OUT_COEFF_7 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT7 */
+ { STB0899_OFF8_EQ_Q_OUT_COEFF_8 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT8 */
+ { STB0899_OFF9_EQ_Q_OUT_COEFF_9 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT9 */
+ { STB0899_OFFa_EQ_Q_OUT_COEFF_10, STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT10*/
+ { 0xffff , 0xffffffff , 0xffffffff },
+};
+
+static const struct stb0899_s1_reg tt3200_stb0899_s1_init_3[] = {
+#if 1
+ { STB0899_DEMOD , 0x00 },
+ { STB0899_RCOMPC , 0xc9 },
+ { STB0899_AGC1CN , 0x41 },
+ { STB0899_AGC1REF , 0x10 },
+ { STB0899_RTC , 0x7a },
+ { STB0899_TMGCFG , 0x4e },
+ { STB0899_AGC2REF , 0x34 },
+ { STB0899_TLSR , 0x84 },
+ { STB0899_CFD , 0xc7 },
+ { STB0899_ACLC , 0x87 },
+ { STB0899_BCLC , 0x94 },
+ { STB0899_EQON , 0x41 },
+ { STB0899_LDT , 0xdd },
+ { STB0899_LDT2 , 0xc9 },
+ { STB0899_EQUALREF , 0xb4 },
+ { STB0899_TMGRAMP , 0x10 },
+ { STB0899_TMGTHD , 0x30 },
+ { STB0899_IDCCOMP , 0xfb },
+ { STB0899_QDCCOMP , 0x03 },
+ { STB0899_POWERI , 0x3b },
+ { STB0899_POWERQ , 0x3d },
+ { STB0899_RCOMP , 0x81 },
+ { STB0899_AGCIQIN , 0x80 },
+ { STB0899_AGC2I1 , 0x04 },
+ { STB0899_AGC2I2 , 0xf5 },
+ { STB0899_TLIR , 0x25 },
+ { STB0899_RTF , 0x80 },
+ { STB0899_DSTATUS , 0x00 },
+ { STB0899_LDI , 0xca },
+ { STB0899_CFRM , 0xf1 },
+ { STB0899_CFRL , 0xf3 },
+ { STB0899_NIRM , 0x2a },
+ { STB0899_NIRL , 0x05 },
+ { STB0899_ISYMB , 0x17 },
+ { STB0899_QSYMB , 0xfa },
+ { STB0899_SFRH , 0x2f },
+ { STB0899_SFRM , 0x68 },
+ { STB0899_SFRL , 0x40 },
+ { STB0899_SFRUPH , 0x2f },
+ { STB0899_SFRUPM , 0x68 },
+ { STB0899_SFRUPL , 0x40 },
+ { STB0899_EQUAI1 , 0xfd },
+ { STB0899_EQUAQ1 , 0x04 },
+ { STB0899_EQUAI2 , 0x0f },
+ { STB0899_EQUAQ2 , 0xff },
+ { STB0899_EQUAI3 , 0xdf },
+ { STB0899_EQUAQ3 , 0xfa },
+ { STB0899_EQUAI4 , 0x37 },
+ { STB0899_EQUAQ4 , 0x0d },
+ { STB0899_EQUAI5 , 0xbd },
+ { STB0899_EQUAQ5 , 0xf7 },
+ { STB0899_DSTATUS2 , 0x00 },
+ { STB0899_VSTATUS , 0x00 },
+ { STB0899_VERROR , 0xff },
+ { STB0899_IQSWAP , 0x2a },
+ { STB0899_ECNT1M , 0x00 },
+ { STB0899_ECNT1L , 0x00 },
+ { STB0899_ECNT2M , 0x00 },
+ { STB0899_ECNT2L , 0x00 },
+ { STB0899_ECNT3M , 0x00 },
+ { STB0899_ECNT3L , 0x00 },
+ { STB0899_FECAUTO1 , 0x06 },
+ { STB0899_FECM , 0x01 },
+ { STB0899_VTH12 , 0xf0 },
+ { STB0899_VTH23 , 0xa0 },
+ { STB0899_VTH34 , 0x78 },
+ { STB0899_VTH56 , 0x4e },
+ { STB0899_VTH67 , 0x48 },
+ { STB0899_VTH78 , 0x38 },
+ { STB0899_PRVIT , 0xff },
+ { STB0899_VITSYNC , 0x19 },
+ { STB0899_RSULC , 0xb1 }, // DVB = 0xb1, DSS = 0xa1
+ { STB0899_TSULC , 0x42 },
+ { STB0899_RSLLC , 0x40 },
+ { STB0899_TSLPL , 0x12 },
+ { STB0899_TSCFGH , 0x0c },
+ { STB0899_TSCFGM , 0x00 },
+ { STB0899_TSCFGL , 0x0c },
+ { STB0899_TSOUT , 0x07 },
+ { STB0899_RSSYNCDEL , 0x00 },
+ { STB0899_TSINHDELH , 0x02 },
+ { STB0899_TSINHDELM , 0x00 },
+ { STB0899_TSINHDELL , 0x00 },
+ { STB0899_TSLLSTKM , 0x00 },
+ { STB0899_TSLLSTKL , 0x00 },
+ { STB0899_TSULSTKM , 0x00 },
+ { STB0899_TSULSTKL , 0xab },
+ { STB0899_PCKLENUL , 0x00 },
+ { STB0899_PCKLENLL , 0xcc },
+ { STB0899_RSPCKLEN , 0xcc },
+ { STB0899_TSSTATUS , 0x80 },
+ { STB0899_ERRCTRL1 , 0xb6 },
+ { STB0899_ERRCTRL2 , 0x96 },
+ { STB0899_ERRCTRL3 , 0x89 },
+ { STB0899_DMONMSK1 , 0x27 },
+ { STB0899_DMONMSK0 , 0x03 },
+ { STB0899_DEMAPVIT , 0x5c },
+ { STB0899_PLPARM , 0x1f },
+ { STB0899_PDELCTRL , 0x48 },
+ { STB0899_PDELCTRL2 , 0x00 },
+ { STB0899_BBHCTRL1 , 0x00 },
+ { STB0899_BBHCTRL2 , 0x00 },
+ { STB0899_HYSTTHRESH , 0x77 },
+ { STB0899_MATCSTM , 0x00 },
+ { STB0899_MATCSTL , 0x00 },
+ { STB0899_UPLCSTM , 0x00 },
+ { STB0899_UPLCSTL , 0x00 },
+ { STB0899_DFLCSTM , 0x00 },
+ { STB0899_DFLCSTL , 0x00 },
+ { STB0899_SYNCCST , 0x00 },
+ { STB0899_SYNCDCSTM , 0x00 },
+ { STB0899_SYNCDCSTL , 0x00 },
+ { STB0899_ISI_ENTRY , 0x00 },
+ { STB0899_ISI_BIT_EN , 0x00 },
+ { STB0899_MATSTRM , 0x00 },
+ { STB0899_MATSTRL , 0x00 },
+ { STB0899_UPLSTRM , 0x00 },
+ { STB0899_UPLSTRL , 0x00 },
+ { STB0899_DFLSTRM , 0x00 },
+ { STB0899_DFLSTRL , 0x00 },
+ { STB0899_SYNCSTR , 0x00 },
+ { STB0899_SYNCDSTRM , 0x00 },
+ { STB0899_SYNCDSTRL , 0x00 },
+ { STB0899_CFGPDELSTATUS1 , 0x10 },
+ { STB0899_CFGPDELSTATUS2 , 0x00 },
+ { STB0899_BBFERRORM , 0x00 },
+ { STB0899_BBFERRORL , 0x00 },
+ { STB0899_UPKTERRORM , 0x00 },
+ { STB0899_UPKTERRORL , 0x00 },
+ { 0xffff , 0xff },
+#else
+ { STB0899_DEMOD , 0x20 /*0x00*/ },
+ { STB0899_RCOMPC , 0xc9 },
+ { STB0899_AGC1CN , 0x01 /*0x41*/ },
+ { STB0899_AGC1REF , 0x10 },
+ { STB0899_RTC , 0x7a },
+ { STB0899_TMGCFG , 0x4e },
+ { STB0899_AGC2REF , 0x34 },
+ { STB0899_TLSR , 0x84 },
+ { STB0899_CFD , 0x47 /*0xc7*/ },
+ { STB0899_ACLC , 0xC8 /*0x87*/ },
+ { STB0899_BCLC , 0xA0 /*0x94*/ },
+ { STB0899_EQON , 0x41 },
+ { STB0899_LDT , 0xdd },
+ { STB0899_LDT2 , 0xc9 },
+ { STB0899_EQUALREF , 0xb4 },
+ { STB0899_TMGRAMP , 0x10 },
+ { STB0899_TMGTHD , 0x30 },
+ { STB0899_IDCCOMP , 0xFF /*0xfb*/ },
+ { STB0899_QDCCOMP , 0x01 /*0x03*/ },
+ { STB0899_POWERI , 0x16 /*0x3b*/ },
+ { STB0899_POWERQ , 0x16 /*0x3d*/ },
+ { STB0899_RCOMP , 0x7B /*0x81*/ },
+ { STB0899_AGCIQIN , 0x80 },
+ { STB0899_AGC2I1 , 0x03 /*0x04*/ },
+ { STB0899_AGC2I2 , 0x1F /*0xf5*/ },
+ { STB0899_TLIR , 0x31 /*0x25*/ },
+ { STB0899_RTF , 0xF2 /*0x80*/ },
+ { STB0899_DSTATUS , 0x08 /*0x00*/ },
+ { STB0899_LDI , 0xB2 /*0xca*/ },
+ { STB0899_CFRM , 0x00 /*0xf1*/ },
+ { STB0899_CFRL , 0x00 /*0xf3*/ },
+ { STB0899_NIRM , 0x2C /*0x2a*/ },
+ { STB0899_NIRL , 0x18 /*0x05*/ },
+ { STB0899_ISYMB , 0x21 /*0x17*/ },
+ { STB0899_QSYMB , 0x00 /*0xfa*/ },
+ { STB0899_SFRH , 0x41 /*0x2f*/ },
+ { STB0899_SFRM , 0x2f /*0x68*/ },
+ { STB0899_SFRL , 0x60 /*0x40*/ },
+ { STB0899_SFRUPH , 0x43 /*0x2f*/ },
+ { STB0899_SFRUPM , 0x24 /*0x68*/ },
+ { STB0899_SFRUPL , 0x00 /*0x40*/ },
+ { STB0899_EQUAI1 , 0x00 /*0xfd*/ },
+ { STB0899_EQUAQ1 , 0x00 /*0x04*/ },
+ { STB0899_EQUAI2 , 0x00 /*0x0f*/ },
+ { STB0899_EQUAQ2 , 0x00 /*0xff*/ },
+ { STB0899_EQUAI3 , 0x00 /*0xdf*/ },
+ { STB0899_EQUAQ3 , 0x00 /*0xfa*/ },
+ { STB0899_EQUAI4 , 0x00 /*0x37*/ },
+ { STB0899_EQUAQ4 , 0x00 /*0x0d*/ },
+ { STB0899_EQUAI5 , 0x00 /*0xbd*/ },
+ { STB0899_EQUAQ5 , 0x00 /*0xf7*/ },
+ { STB0899_DSTATUS2 , 0x40 /*0x00*/ },
+ { STB0899_VSTATUS , 0x00 },
+ { STB0899_VERROR , 0xff },
+ { STB0899_IQSWAP , 0x20 /*0x2a*/ },
+ { STB0899_ECNT1M , 0x00 },
+ { STB0899_ECNT1L , 0x02 /*0x00*/ },
+ { STB0899_ECNT2M , 0x00 },
+ { STB0899_ECNT2L , 0x00 },
+ { STB0899_ECNT3M , 0x3c /*0x00*/ },
+ { STB0899_ECNT3L , 0xF6 /*0x00*/ },
+ { STB0899_FECAUTO1 , 0x06 },
+ { STB0899_FECM , 0x00 /*0x01*/ },
+ { STB0899_VTH12 , 0xb0 /*0xf0*/ },
+ { STB0899_VTH23 , 0x7a /*0xa0*/ },
+ { STB0899_VTH34 , 0x58 /*0x78*/ },
+ { STB0899_VTH56 , 0x38 /*0x4e*/ },
+ { STB0899_VTH67 , 0x34 /*0x48*/ },
+ { STB0899_VTH78 , 0x24 /*0x38*/ },
+ { STB0899_PRVIT , 0xff },
+ { STB0899_VITSYNC , 0x19 },
+ { STB0899_RSULC , 0xb1 }, // DVB = 0xb1, DSS = 0xa1
+ { STB0899_TSULC , 0x42 },
+ { STB0899_RSLLC , 0x40 },
+ { STB0899_TSLPL , 0x12 },
+ { STB0899_TSCFGH , 0x00 /*0x0c*/ }, //0x0c
+ { STB0899_TSCFGM , 0x5f /*0x00*/ },
+ { STB0899_TSCFGL , 0x0c }, //0x0c
+ { STB0899_TSOUT , 0x07 },
+ { STB0899_RSSYNCDEL , 0x00 },
+ { STB0899_TSINHDELH , 0x02 },
+ { STB0899_TSINHDELM , 0x00 },
+ { STB0899_TSINHDELL , 0x00 },
+ { STB0899_TSLLSTKM , 0x0e /*0x00*/ },
+ { STB0899_TSLLSTKL , 0xe4 /*0x00*/ },
+ { STB0899_TSULSTKM , 0x00 },
+ { STB0899_TSULSTKL , 0x00 /*0xab*/ },
+ { STB0899_PCKLENUL , 0xbc /*0x00*/ },
+ { STB0899_PCKLENLL , 0xcc },
+ { STB0899_RSPCKLEN , 0x83 /*0xcc*/ },
+ { STB0899_TSSTATUS , 0xd8 /*0x80*/ },
+ { STB0899_ERRCTRL1 , 0xb6 },
+ { STB0899_ERRCTRL2 , 0x96 },
+ { STB0899_ERRCTRL3 , 0x89 },
+ { STB0899_DMONMSK1 , 0x27 },
+ { STB0899_DMONMSK0 , 0x03 },
+ { STB0899_DEMAPVIT , 0x3c /*0x5c*/ },
+ { STB0899_PLPARM , 0x35 /*0x1f*/ },
+ { STB0899_PDELCTRL , 0x48 },
+ { STB0899_PDELCTRL2 , 0x00 },
+ { STB0899_BBHCTRL1 , 0x00 },
+ { STB0899_BBHCTRL2 , 0x00 },
+ { STB0899_HYSTTHRESH , 0x77 },
+ { STB0899_MATCSTM , 0x00 },
+ { STB0899_MATCSTL , 0x00 },
+ { STB0899_UPLCSTM , 0x00 },
+ { STB0899_UPLCSTL , 0x00 },
+ { STB0899_DFLCSTM , 0x00 },
+ { STB0899_DFLCSTL , 0x00 },
+ { STB0899_SYNCCST , 0x00 },
+ { STB0899_SYNCDCSTM , 0x00 },
+ { STB0899_SYNCDCSTL , 0x00 },
+ { STB0899_ISI_ENTRY , 0x00 },
+ { STB0899_ISI_BIT_EN , 0x00 },
+ { STB0899_MATSTRM , 0xf0 /*0x00*/ },
+ { STB0899_MATSTRL , 0x01 /*0x00*/ },
+ { STB0899_UPLSTRM , 0x05 /*0x00*/ },
+ { STB0899_UPLSTRL , 0xe0 /*0x00*/ },
+ { STB0899_DFLSTRM , 0x7d /*0x00*/ },
+ { STB0899_DFLSTRL , 0x80 /*0x00*/ },
+ { STB0899_SYNCSTR , 0x47 /*0x00*/ },
+ { STB0899_SYNCDSTRM , 0x00 },
+ { STB0899_SYNCDSTRL , 0x78 /*0x00*/ },
+ { STB0899_CFGPDELSTATUS1 , 0x1D /*0x10*/ },
+ { STB0899_CFGPDELSTATUS2 , 0x0e /*0x00*/ },
+ { STB0899_BBFERRORM , 0x00 },
+ { STB0899_BBFERRORL , 0x03 /*0x00*/ },
+ { STB0899_UPKTERRORM , 0x00 },
+ { STB0899_UPKTERRORL , 0x2c /*0x00*/ },
+ { 0xffff , 0xff },
+#endif
+};
+
+static const struct stb0899_s2_reg tt3200_stb0899_s2_init_4[] = {
+ { STB0899_OFF0_BLOCK_LNGTH , STB0899_BASE_BLOCK_LNGTH , 0x00000008 }, /* BLOCKLNGTH */
+ { STB0899_OFF0_ROW_STR , STB0899_BASE_ROW_STR , 0x000000b4 }, /* ROWSTR */
+ { STB0899_OFF0_BN_END_ADDR , STB0899_BASE_BN_END_ADDR , 0x000004b5 }, /* BNANDADDR */
+ { STB0899_OFF0_CN_END_ADDR , STB0899_BASE_CN_END_ADDR , 0x00000b4b }, /* CNANDADDR */
+ { STB0899_OFF0_INFO_LENGTH , STB0899_BASE_INFO_LENGTH , 0x00000078 }, /* INFOLENGTH */
+ { STB0899_OFF0_BOT_ADDR , STB0899_BASE_BOT_ADDR , 0x000001e0 }, /* BOT_ADDR */
+ { STB0899_OFF0_BCH_BLK_LN , STB0899_BASE_BCH_BLK_LN , 0x0000a8c0 }, /* BCHBLKLN */
+ { STB0899_OFF0_BCH_T , STB0899_BASE_BCH_T , 0x0000000c }, /* BCHT */
+ { STB0899_OFF0_CNFG_MODE , STB0899_BASE_CNFG_MODE , 0x00000001 }, /* CNFGMODE */
+ { STB0899_OFF0_LDPC_STAT , STB0899_BASE_LDPC_STAT , 0x0000000d }, /* LDPCSTAT */
+ { STB0899_OFF0_ITER_SCALE , STB0899_BASE_ITER_SCALE , 0x00000040 }, /* ITERSCALE */
+ { STB0899_OFF0_INPUT_MODE , STB0899_BASE_INPUT_MODE , 0x00000000 }, /* INPUTMODE */
+ { STB0899_OFF0_LDPCDECRST , STB0899_BASE_LDPCDECRST , 0x00000000 }, /* LDPCDECRST */
+ { STB0899_OFF0_CLK_PER_BYTE_RW , STB0899_BASE_CLK_PER_BYTE_RW , 0x00000008 }, /* CLKPERBYTE */
+ { STB0899_OFF0_BCH_ERRORS , STB0899_BASE_BCH_ERRORS , 0x00000000 }, /* BCHERRORS */
+ { STB0899_OFF0_LDPC_ERRORS , STB0899_BASE_LDPC_ERRORS , 0x00000000 }, /* LDPCERRORS */
+ { STB0899_OFF0_BCH_MODE , STB0899_BASE_BCH_MODE , 0x00000000 }, /* BCHMODE */
+ { STB0899_OFF0_ERR_ACC_PER , STB0899_BASE_ERR_ACC_PER , 0x00000008 }, /* ERRACCPER */
+ { STB0899_OFF0_BCH_ERR_ACC , STB0899_BASE_BCH_ERR_ACC , 0x00000000 }, /* BCHERRACC */
+ { STB0899_OFF0_FEC_TP_SEL , STB0899_BASE_FEC_TP_SEL , 0x00000000 }, /* FECTPSEL */
+ { 0xffff , 0xffffffff , 0xffffffff },
+};
+static const struct stb0899_s1_reg tt3200_stb0899_s1_init_5[] = {
+ { STB0899_TSTCK , 0x00 },
+ { STB0899_TSTRES , 0x00 },
+ { STB0899_TSTOUT , 0x00 },
+ { STB0899_TSTIN , 0x00 },
+ { STB0899_TSTSYS , 0x00 },
+ { STB0899_TSTCHIP , 0x00 },
+ { STB0899_TSTFREE , 0x00 },
+ { STB0899_TSTI2C , 0x00 },
+ { STB0899_BITSPEEDM , 0x00 },
+ { STB0899_BITSPEEDL , 0x00 },
+ { STB0899_TBUSBIT , 0x00 },
+ { STB0899_TSTDIS , 0x00 },
+ { STB0899_TSTDISRX , 0x00 },
+ { STB0899_TSTJETON , 0x00 },
+ { STB0899_TSTDCADJ , 0x00 },
+ { STB0899_TSTAGC1 , 0x00 },
+ { STB0899_TSTAGC1N , 0x00 },
+ { STB0899_TSTPOLYPH , 0x00 },
+ { STB0899_TSTR , 0x00 },
+ { STB0899_TSTAGC2 , 0x00 },
+ { STB0899_TSTCTL1 , 0x00 },
+ { STB0899_TSTCTL2 , 0x00 },
+ { STB0899_TSTCTL3 , 0x00 },
+ { STB0899_TSTDEMAP , 0x00 },
+ { STB0899_TSTDEMAP2 , 0x00 },
+ { STB0899_TSTDEMMON , 0x00 },
+ { STB0899_TSTRATE , 0x00 },
+ { STB0899_TSTSELOUT , 0x00 },
+ { STB0899_TSYNC , 0x00 },
+ { STB0899_TSTERR , 0x00 },
+ { STB0899_TSTRAM1 , 0x00 },
+ { STB0899_TSTVSELOUT , 0x00 },
+ { STB0899_TSTFORCEIN , 0x00 },
+ { STB0899_TSTRS1 , 0x00 },
+ { STB0899_TSTRS2 , 0x00 },
+ { STB0899_TSTRS3 , 0x00 },
+ { STB0899_GHOSTREG , 0x81 },
+ { 0xffff , 0xff },
+};
+
+static int tt3200_set_frequency(struct dvb_frontend *fe, u32 frequency)
+{
+ struct budget* budget = (struct budget*) fe->dvb->priv;
+ struct tuner_state stb6100_tuner_state;
+ if ( budget->dvb_frontend->ops.tuner_ops.set_state ) {
+
+ stb6100_tuner_state.frequency = frequency;
+
+// printk("%s frequency=%d\n",__func__,frequency);
+
+ budget->dvb_frontend->ops.tuner_ops.set_state(
+ fe,DVBFE_TUNER_FREQUENCY,
+ &stb6100_tuner_state);
+
+ /* FIXME !
+ * This is just a hack because dvb-pll is too rigid
+ * will need to adjust dvb-pll to avoid unpleasant
+ * issues like this !
+ */
+ msleep(200);
+ }
+
+ return 0;
+}
+
+static int tt3200_get_frequency(struct dvb_frontend *fe, u32 *frequency)
+{
+ struct budget* budget = (struct budget*) fe->dvb->priv;
+ struct tuner_state stb6100_tuner_state;
+ *frequency = 0;
+ if ( budget->dvb_frontend->ops.tuner_ops.get_state ) {
+
+ budget->dvb_frontend->ops.tuner_ops.get_state(
+ fe,DVBFE_TUNER_FREQUENCY,
+ &stb6100_tuner_state);
+
+ *frequency = stb6100_tuner_state.frequency;
+ }
+
+ return 0;
+}
+
+static int tt3200_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
+{
+ struct budget* budget = (struct budget*) fe->dvb->priv;
+ struct tuner_state stb6100_tuner_state;
+ if ( budget->dvb_frontend->ops.tuner_ops.set_state ) {
+
+ stb6100_tuner_state.bandwidth = bandwidth;
+
+// printk("%s bandwidth=%d\n",__func__,bandwidth);
+
+ budget->dvb_frontend->ops.tuner_ops.set_state(
+ fe,DVBFE_TUNER_BANDWIDTH,
+ &stb6100_tuner_state);
+
+ /* FIXME !
+ * This is just a hack because dvb-pll is too rigid
+ * will need to adjust dvb-pll to avoid unpleasant
+ * issues like this !
+ */
+// msleep(200);
+ }
+ return 0;
+}
+
+static int tt3200_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
+{
+ struct budget* budget = (struct budget*) fe->dvb->priv;
+ struct tuner_state stb6100_tuner_state;
+
+ *bandwidth = 0;
+ if ( budget->dvb_frontend->ops.tuner_ops.get_state ) {
+
+ budget->dvb_frontend->ops.tuner_ops.get_state(
+ fe,DVBFE_TUNER_BANDWIDTH,
+ &stb6100_tuner_state);
+
+ *bandwidth = stb6100_tuner_state.bandwidth;
+
+// printk("%s bandwidth=%d\n",__func__,*bandwidth);
+
+ }
+
+ return 0;
+}
+
+/*
+static int tt3200_set_params(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
+{
+ printk("%s frequency=%d\n",__func__,p->frequency);
+ return tt3200_set_frequency(fe,p->frequency);
+}
+*/
+
+#define KNC1_DVBS2_ESNO_AVE 3
+#define KNC1_DVBS2_ESNO_QUANT 32
+#define KNC1_DVBS2_AVFRAMES_COARSE 10
+#define KNC1_DVBS2_AVFRAMES_FINE 20
+#define KNC1_DVBS2_MISS_THRESHOLD 6
+#define KNC1_DVBS2_UWP_THRESHOLD_ACQ 1125
+#define KNC1_DVBS2_UWP_THRESHOLD_TRACK 758
+#define KNC1_DVBS2_UWP_THRESHOLD_SOF 1350
+#define KNC1_DVBS2_SOF_SEARCH_TIMEOUT 1664100
+
+#define KNC1_DVBS2_BTR_NCO_BITS 28
+#define KNC1_DVBS2_BTR_GAIN_SHIFT_OFFSET 15
+#define KNC1_DVBS2_CRL_NCO_BITS 30
+#define KNC1_DVBS2_LDPC_MAX_ITER 70
+
+static struct stb0899_config tt3200_config = {
+ .init_dev = tt3200_stb0899_s1_init_1,
+ .init_s2_demod = tt3200_stb0899_s2_init_2,
+ .init_s1_demod = tt3200_stb0899_s1_init_3,
+ .init_s2_fec = tt3200_stb0899_s2_init_4,
+ .init_tst = tt3200_stb0899_s1_init_5,
+
+ .demod_address = 0x68,
+// .ts_output_mode = STB0899_OUT_PARALLEL, /* types = SERIAL/PARALLEL */
+ .block_sync_mode = STB0899_SYNC_FORCED, /* DSS, SYNC_FORCED/UNSYNCED */
+// .ts_pfbit_toggle = STB0899_MPEG_NORMAL, /* DirecTV, MPEG toggling seq */
+
+ .xtal_freq = 27000000,
+// .inversion = 1,
+ .inversion = 2,
+
+ .esno_ave = KNC1_DVBS2_ESNO_AVE,
+ .esno_quant = KNC1_DVBS2_ESNO_QUANT,
+ .avframes_coarse = KNC1_DVBS2_AVFRAMES_COARSE,
+ .avframes_fine = KNC1_DVBS2_AVFRAMES_FINE,
+ .miss_threshold = KNC1_DVBS2_MISS_THRESHOLD,
+ .uwp_threshold_acq = KNC1_DVBS2_UWP_THRESHOLD_ACQ,
+ .uwp_threshold_track = KNC1_DVBS2_UWP_THRESHOLD_TRACK,
+ .uwp_threshold_sof = KNC1_DVBS2_UWP_THRESHOLD_SOF,
+ .sof_search_timeout = KNC1_DVBS2_SOF_SEARCH_TIMEOUT,
+
+ .btr_nco_bits = KNC1_DVBS2_BTR_NCO_BITS,
+ .btr_gain_shift_offset = KNC1_DVBS2_BTR_GAIN_SHIFT_OFFSET,
+ .crl_nco_bits = KNC1_DVBS2_CRL_NCO_BITS,
+ .ldpc_max_iter = KNC1_DVBS2_LDPC_MAX_ITER,
+
+ .tuner_get_frequency = tt3200_get_frequency,
+ .tuner_set_frequency = tt3200_set_frequency,
+ .tuner_set_bandwidth = tt3200_set_bandwidth,
+ .tuner_get_bandwidth = tt3200_get_bandwidth,
+};
+
+struct stb6100_config tt3200_stb6100_config = {
+ .tuner_address = 0x60, /* I2C-Adresse */
+ .refclock = 27000, /* kHz */
+// .refclock = 27000000,
+};
static void frontend_init(struct budget_ci *budget_ci)
@@ -1156,6 +2004,32 @@ static void frontend_init(struct budget_
}
break;
+
+ case 0x1019: // TT S2-3200 PCI
+ // gpio2 is connected to CLB - reset it + leave it high
+ saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTLO);
+ msleep(1);
+ saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTHI);
+ msleep(1);
+
+ budget_ci->budget.dvb_frontend = dvb_attach(stb0899_attach, &tt3200_config, &budget_ci->budget.i2c_adap);
+ if (budget_ci->budget.dvb_frontend) {
+ if (dvb_attach(stb6100_attach, budget_ci->budget.dvb_frontend, &tt3200_stb6100_config, &budget_ci->budget.i2c_adap)) {
+ if (dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, LNBP21_LLC, 0) == NULL) {
+ printk("%s: No LNBP21 found!\n", __FUNCTION__);
+ if (budget_ci->budget.dvb_frontend->ops.tuner_ops.release)
+ budget_ci->budget.dvb_frontend->ops.tuner_ops.release(budget_ci->budget.dvb_frontend);
+ dvb_frontend_detach(budget_ci->budget.dvb_frontend);
+ budget_ci->budget.dvb_frontend = NULL;
+ }
+ } else {
+ printk("%s: No STB6100 found!\n", __FUNCTION__);
+ dvb_frontend_detach(budget_ci->budget.dvb_frontend);
+ budget_ci->budget.dvb_frontend = NULL;
+ }
+ }
+ break;
+
}
if (budget_ci->budget.dvb_frontend == NULL) {
@@ -1244,6 +2118,7 @@ MAKE_BUDGET_INFO(ttbci, "TT-Budget/WinTV
MAKE_BUDGET_INFO(ttbt2, "TT-Budget/WinTV-NOVA-T PCI", BUDGET_TT);
MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT);
MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT);
+MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT3200);
static struct pci_device_id pci_tbl[] = {
MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c),
@@ -1252,6 +2127,7 @@ static struct pci_device_id pci_tbl[] =
MAKE_EXTENSION_PCI(ttbt2, 0x13c2, 0x1011),
MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012),
MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017),
+ MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019),
{
.vendor = 0,
}
diff -urNp v4l-dvb.org/linux/drivers/media/dvb/ttpci/budget.h v4l-dvb/linux/drivers/media/dvb/ttpci/budget.h
--- v4l-dvb.org/linux/drivers/media/dvb/ttpci/budget.h 2007-02-24 13:07:53.000000000 +0100
+++ v4l-dvb/linux/drivers/media/dvb/ttpci/budget.h 2007-05-21 19:16:42.000000000 +0200
@@ -108,6 +108,7 @@ static struct saa7146_pci_extension_data
#define BUDGET_KNC1TP 13
#define BUDGET_TVSTAR 14
#define BUDGET_KNC1S2 15
+#define BUDGET_TT3200 16
#define BUDGET_VIDEO_PORTA 0
#define BUDGET_VIDEO_PORTB 1
diff -urNp v4l-dvb.org/v4l-scripts-make_myconfig.pl v4l-dvb/v4l-scripts-make_myconfig.pl
--- v4l-dvb.org/v4l-scripts-make_myconfig.pl 1970-01-01 01:00:00.000000000 +0100
+++ v4l-dvb/v4l-scripts-make_myconfig.pl 2007-05-21 19:16:42.000000000 +0200
@@ -0,0 +1,58 @@
+#!/usr/bin/perl
+
+# The purpose of this script is to produce a file named '.myconfig', in
+# the same style as the '.config' file. Except .myconfig has disabled
+# options explicitly set to 'n' rather than just omitted. This is to
+# make sure they override any corresponding options that may be turned on
+# in the Kernel's config files.
+# The .myconfig file is what will be included in the v4l-dvb Makefile
+# to control which drivers are built.
+
+my %config = ();
+my %allconfig = ();
+
+open IN,".config";
+while (<IN>) {
+ if (m/\s*(\w+)=\s*(\S*)/) {
+#printf "%s=%s\n",$1,$2;
+ $config { $1 } = $2;
+ }
+}
+close IN;
+
+# Build table of _all_ bool and tristate config variables
+my $key = 0;
+open IN,"Kconfig";
+while (<IN>) {
+ if (/^config\s+(\w+)\s*$/) {
+ $key == 0 or die "Couldn't find type of config '$key'";
+ $key = "CONFIG_$1";
+ } elsif (/^\s+bool(ean)?\s/) {
+ $allconfig{$key} = 'bool';
+ $key = 0;
+ } elsif (/^\s+tristate\s/) {
+ $allconfig{$key} = 'tristate';
+ $key = 0;
+ } elsif (/^\s+(int|hex|string)\s/) {
+ $allconfig{$key} = 'data';
+ $key = 0;
+ }
+}
+close IN;
+
+exists $allconfig{0} and die "Unable to correctly parse Kconfig file";
+
+# Produce output for including in a Makefile
+# Explicitly set bool/tri options that didn't appear in .config to n
+# 'data' options are only output if they appeared in .config
+open OUT,">.myconfig";
+while ( my ($key, $value) = each(%allconfig) ) {
+ if ($value eq 'data') {
+ next unless (exists $config{$key});
+ $value = $config{$key};
+ } else {
+ $value = exists $config{$key} ? $config{$key} : 'n';
+ }
+ printf OUT "%-44s := %s\n",$key,$value;
+}
+close OUT;
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