ok, can one of the tuner specialists (Andrew maybe :) check the
filter readings from the attached diagnostics patch
on qam256 with FuSi FF dvb-c D1121?
thx.
for me they look ok. whether its provider signal crap
or siemens was right not to assure > 64qam with this
chip on the FuSi card: manual: technical specs page:
A26361-D1121-Z101-DE.pdf
maybe tuner or if circuit fscks higher qam signals, i see no problem
with the ves1820...
Aug 3 20:32:52 tom1 kernel: ves1820: Verbose Status:
Aug 3 20:32:52 tom1 kernel: ves1820: VAFC 0
Aug 3 20:32:52 tom1 kernel: ves1820: VAGC 0xff
Aug 3 20:32:52 tom1 kernel: ves1820: AGCCONF 0x13
Aug 3 20:32:52 tom1 kernel: ves1820: AGCREF 0x13
Aug 3 20:32:52 tom1 kernel: ves1820: PWMREF 0x13
Aug 3 20:32:52 tom1 kernel: ves1820: MSE 0x14
Aug 3 20:32:52 tom1 kernel: ves1820: BER-RANGE 0
Aug 3 20:32:52 tom1 kernel: ves1820: SATNYQ 0x00
Aug 3 20:32:52 tom1 kernel: ves1820: SATADC 0x00
Aug 3 20:32:52 tom1 kernel: ves1820: HALFADC 0x96
Aug 3 20:32:52 tom1 kernel: ves1820: SATDEC1 0x00
Aug 3 20:32:52 tom1 kernel: ves1820: SATDEC2 0x00
Aug 3 20:32:52 tom1 kernel: ves1820: SATDEC3 0x06
Aug 3 20:32:52 tom1 kernel: ves1820: CLKOFFSET 0x13
Aug 3 20:32:52 tom1 kernel: ves1820: SATAAF 0x00
Aug 3 20:32:53 tom1 kernel:
Aug 3 20:32:53 tom1 kernel: ves1820: Verbose Status:
Aug 3 20:32:53 tom1 kernel: ves1820: VAFC 0
Aug 3 20:32:53 tom1 kernel: ves1820: VAGC 0xff
Aug 3 20:32:53 tom1 kernel: ves1820: AGCCONF 0x13
Aug 3 20:32:53 tom1 kernel: ves1820: AGCREF 0x13
Aug 3 20:32:53 tom1 kernel: ves1820: PWMREF 0x13
Aug 3 20:32:53 tom1 kernel: ves1820: MSE 0x1a
Aug 3 20:32:53 tom1 kernel: ves1820: BER-RANGE 0
Aug 3 20:32:53 tom1 kernel: ves1820: SATNYQ 0x00
Aug 3 20:32:53 tom1 kernel: ves1820: SATADC 0x00
Aug 3 20:32:53 tom1 kernel: ves1820: HALFADC 0x6b
Aug 3 20:32:53 tom1 kernel: ves1820: SATDEC1 0x00
Aug 3 20:32:53 tom1 kernel: ves1820: SATDEC2 0x00
Aug 3 20:32:53 tom1 kernel: ves1820: SATDEC3 0x04
Aug 3 20:32:53 tom1 kernel: ves1820: CLKOFFSET 0x13
Aug 3 20:32:53 tom1 kernel: ves1820: SATAAF 0x00
Aug 3 20:32:24 tom1 kernel: ves1820: Verbose Status:
Aug 3 20:32:24 tom1 kernel: ves1820: VAFC 0
Aug 3 20:32:24 tom1 kernel: ves1820: VAGC 0xff
Aug 3 20:32:24 tom1 kernel: ves1820: AGCCONF 0x13
Aug 3 20:32:24 tom1 kernel: ves1820: AGCREF 0x13
Aug 3 20:32:24 tom1 kernel: ves1820: PWMREF 0x13
Aug 3 20:32:24 tom1 kernel: ves1820: MSE 0x13
Aug 3 20:32:24 tom1 kernel: ves1820: BER-RANGE 0
Aug 3 20:32:24 tom1 kernel: ves1820: SATNYQ 0x00
Aug 3 20:32:24 tom1 kernel: ves1820: SATADC 0x00
Aug 3 20:32:24 tom1 kernel: ves1820: HALFADC 0x78
Aug 3 20:32:24 tom1 kernel: ves1820: SATDEC1 0x00
Aug 3 20:32:24 tom1 kernel: ves1820: SATDEC2 0x00
Aug 3 20:32:24 tom1 kernel: ves1820: SATDEC3 0x04
Aug 3 20:32:24 tom1 kernel: ves1820: CLKOFFSET 0x13
Aug 3 20:32:24 tom1 kernel: ves1820: SATAAF 0x00
Aug 3 20:32:25 tom1 kernel:
--- ves1820.c-orig 2006-07-25 05:36:01.000000000 +0200
+++ ves1820.c 2006-08-03 19:30:19.000000000 +0200
@@ -47,6 +47,7 @@
static int verbose;
+static int screw;
static u8 ves1820_inittab[] = {
0x69, 0x6A, 0x93, 0x12, 0x12, 0x46, 0x26, 0x1A,
@@ -197,6 +198,8 @@
ves1820_writereg(state, 0, 0);
+ ves1820_inittab[2] = (u8)screw; //X X X XXXXXXXXXXXXXX X X X
+
for (i = 0; i < sizeof(ves1820_inittab); i++)
ves1820_writereg(state, i, ves1820_inittab[i]);
if (state->config->selagc)
@@ -219,6 +222,7 @@
static const u8 reg0x08[] = { 162, 116, 67, 52, 35 };
static const u8 reg0x09[] = { 145, 150, 106, 126, 107 };
int real_qam = p->u.qam.modulation - QAM_16;
+// reg0x08[4] = (u8)screw;
if (real_qam < 0 || real_qam > 4)
return -EINVAL;
@@ -227,10 +231,10 @@
ves1820_set_symbolrate(state, p->u.qam.symbol_rate);
ves1820_writereg(state, 0x34, state->pwm);
- ves1820_writereg(state, 0x01, reg0x01[real_qam]);
- ves1820_writereg(state, 0x05, reg0x05[real_qam]);
- ves1820_writereg(state, 0x08, reg0x08[real_qam]);
- ves1820_writereg(state, 0x09, reg0x09[real_qam]);
+ ves1820_writereg(state, 0x01, reg0x01[real_qam]); //agcref
+ ves1820_writereg(state, 0x05, reg0x05[real_qam]); //lock threshold
+ ves1820_writereg(state, 0x08, reg0x08[real_qam]); //tracking/aqui switch
+ ves1820_writereg(state, 0x09, reg0x09[real_qam]); //equalizer
ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);
ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0));
@@ -240,26 +244,57 @@
static int ves1820_read_status(struct dvb_frontend* fe, fe_status_t* status)
{
struct ves1820_state* state = fe->demodulator_priv;
- int sync;
-
+ u8 sync = ves1820_readreg(state, 0x11);
+ u8 vagc = ves1820_readreg(state, 0x17);
+ u8 agcconf = ves1820_readreg(state, 0x02);
+ u8 agcref = ves1820_readreg(state, 0x01);
+ u8 mse = ves1820_readreg(state, 0x18);
+ u8 pwmref = ves1820_readreg(state, 0x34);
+ u8 satnyq = ves1820_readreg(state, 0x21);
+ u8 satadc = ves1820_readreg(state, 0x22);
+ u8 halfadc = ves1820_readreg(state, 0x23);
+ u8 satdec1 = ves1820_readreg(state, 0x24);
+ u8 satdec2 = ves1820_readreg(state, 0x25);
+ u8 satdec3 = ves1820_readreg(state, 0x26);
+ u8 ckoffset = ves1820_readreg(state, 0x1d);
+ u8 sataaf = ves1820_readreg(state, 0x27);
+ s8 vafc = ves1820_readreg(state, 0x19);
*status = 0;
- sync = ves1820_readreg(state, 0x11);
-
- if (sync & 1)
+
+ if (sync & 1) {
*status |= FE_HAS_SIGNAL;
+ *status |= FE_HAS_VITERBI;
+ }
if (sync & 2)
*status |= FE_HAS_CARRIER;
- if (sync & 2) /* XXX FIXME! */
- *status |= FE_HAS_VITERBI;
-
if (sync & 4)
*status |= FE_HAS_SYNC;
if (sync & 8)
*status |= FE_HAS_LOCK;
+ if (verbose) {
+ printk("\n ves1820: Verbose Status: \n");
+ if (sync & 64) printk("ves1820: NODVB The framing of the Stream is not DVB compliant! \n");
+ printk("ves1820: VAFC %d \n", vafc);
+ printk("ves1820: VAGC 0x%02x \n", vagc);
+ printk("ves1820: AGCCONF 0x%02x \n", agcconf);
+ printk("ves1820: AGCREF 0x%02x \n", agcref);
+ printk("ves1820: PWMREF 0x%02x \n", pwmref);
+ printk("ves1820: MSE 0x%02x \n", mse);
+ printk("ves1820: BER-RANGE %d \n", !(sync >> 4));
+ printk("ves1820: SATNYQ 0x%02x \n", satnyq);
+ printk("ves1820: SATADC 0x%02x \n", satadc);
+ printk("ves1820: HALFADC 0x%02x \n", halfadc);
+ printk("ves1820: SATDEC1 0x%02x \n", satdec1);
+ printk("ves1820: SATDEC2 0x%02x \n", satdec2);
+ printk("ves1820: SATDEC3 0x%02x \n", satdec3);
+ printk("ves1820: CLKOFFSET 0x%02x \n", ckoffset);
+ printk("ves1820: SATAAF 0x%02x \n", sataaf);
+
+ }
return 0;
}
@@ -313,11 +348,8 @@
static int ves1820_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
{
struct ves1820_state* state = fe->demodulator_priv;
- int sync;
- s8 afc = 0;
-
- sync = ves1820_readreg(state, 0x11);
- afc = ves1820_readreg(state, 0x19);
+ u8 sync = ves1820_readreg(state, 0x11);
+ s8 afc = ves1820_readreg(state, 0x19);
if (verbose) {
/* AFC only valid when carrier has been recovered */
printk(sync & 2 ? "ves1820: AFC (%d) %dHz\n" :
@@ -384,14 +416,18 @@
state->reg0 = ves1820_inittab[0];
state->config = config;
state->i2c = i2c;
- state->pwm = pwm;
+ state->pwm = 0x54; //pwm 0x54 FuSi
/* check if the demod is there */
- if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70)
+ u8 id = ves1820_readreg(state, 0x1a);
+ if ((id & 0xf0) != 0x70)
goto error;
-
- if (verbose)
+ else
+ if (verbose) {
+ printk("ves1820: Detected Chip Version 0x%02x\n", id);
printk("ves1820: pwm=0x%02x\n", state->pwm);
+ printk("ves1820: screw=0x%02x\n", screw);
+ }
state->ops.info.symbol_rate_min = (state->config->xin / 2) / 64; /* SACLK/64 == (XIN/2)/64 */
state->ops.info.symbol_rate_max = (state->config->xin / 2) / 4; /* SACLK/4 */
@@ -440,6 +476,8 @@
module_param(verbose, int, 0644);
MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");
+module_param(screw, int, 0644);
+MODULE_PARM_DESC(screw, "adapting to signal of crap cable-providers");
MODULE_DESCRIPTION("VLSI VES1820 DVB-C Demodulator driver");
MODULE_AUTHOR("Ralph Metzler, Holger Waechtler");
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