On 23/02/15 18:31, Hartley Sweeten wrote:
On Monday, February 23, 2015 11:06 AM, Ian Abbott wrote:
On 20/02/15 23:04, H Hartley Sweeten wrote:
+ unsigned int val;
+
+ switch (i8254->iosize) {
+ default:
+ case I8254_IO8:
+ if (i8254->mmio)
+ val = readb(i8254->mmio + reg_offset);
+ else
+ val = inb(i8254->iobase + reg_offset);
+ break;
+ case I8254_IO16:
+ if (i8254->mmio)
+ val = readw(i8254->mmio + reg_offset);
+ else
+ val = inw(i8254->iobase + reg_offset);
+ break;
+ case I8254_IO32:
+ if (i8254->mmio)
+ val = readl(i8254->mmio + reg_offset);
+ else
+ val = inl(i8254->iobase + reg_offset);
+ break;
+ }
+ return val;
Only the bottom 8 bits of the returned value are valid, so it ought to
be ANDed with 0xff.
True. None of the current implementations do the masking but it
wouldn't hurt. I'll add this in the next spin.
The current implementations all do 8-bit reads, don't they? Well, apart
from adv_pci1710 which does 16-bit reads and ANDs the values with 0xff.
--
-=( Ian Abbott @ MEV Ltd. E-mail: <abbotti@xxxxxxxxx> )=-
-=( Web: http://www.mev.co.uk/ )=-
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