On Wed, 2014-12-03 at 21:30 +0000, Sean Cleator wrote:
> A patch to fix the rest of the long line warnings in the dgnc_cls.h file
> found by the checkpatch.pl tool
checkpatch is a brainless little tool.
You should prefer to develop a readable style rather than
pay too close attention to precisely what checkpatch says.
fyi: There is this warning in the file:
* NOTE: THIS IS A SHARED HEADER. DO NOT CHANGE CODING STYLE!!!
I would have done changes like this:
---
drivers/staging/dgnc/dgnc_cls.h | 45 ++++++++++++++++++++---------------------
1 file changed, 22 insertions(+), 23 deletions(-)
diff --git a/drivers/staging/dgnc/dgnc_cls.h b/drivers/staging/dgnc/dgnc_cls.h
index 465d79a..db05aed 100644
--- a/drivers/staging/dgnc/dgnc_cls.h
+++ b/drivers/staging/dgnc/dgnc_cls.h
@@ -25,25 +25,24 @@
#include "dgnc_types.h"
-
-/************************************************************************
- * Per channel/port Classic UART structure *
- ************************************************************************
- * Base Structure Entries Usage Meanings to Host *
- * *
- * W = read write R = read only *
- * U = Unused. *
- ************************************************************************/
+/*
+ * Per channel/port classic UART registers structure
+ *
+ * Base structure entries usage - meaning to host:
+ * W = read write
+ * R = read only
+ * U = unused
+ */
struct cls_uart_struct {
- u8 txrx; /* WR RHR/THR - Holding Reg */
- u8 ier; /* WR IER - Interrupt Enable Reg */
- u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
- u8 lcr; /* WR LCR - Line Control Reg */
- u8 mcr; /* WR MCR - Modem Control Reg */
- u8 lsr; /* WR LSR - Line Status Reg */
- u8 msr; /* WR MSR - Modem Status Reg */
- u8 spr; /* WR SPR - Scratch Pad Reg */
+ u8 txrx; /* WR RHR/THR - Holding */
+ u8 ier; /* WR IER - Interrupt Enable */
+ u8 isr_fcr; /* WR ISR/FCR - Interrupt Status / Fifo Control */
+ u8 lcr; /* WR LCR - Line Control */
+ u8 mcr; /* WR MCR - Modem Control */
+ u8 lsr; /* WR LSR - Line Status */
+ u8 msr; /* WR MSR - Modem Status */
+ u8 spr; /* WR SPR - Scratch Pad */
};
/* Where to read the interrupt register (8bits) */
@@ -61,12 +60,12 @@ struct cls_uart_struct {
#define UART_16654_FCR_RXTRIGGER_56 0x80
#define UART_16654_FCR_RXTRIGGER_60 0xC0
-#define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */
-#define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
+#define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */
+#define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
/*
- * These are the EXTENDED definitions for the Exar 654's Interrupt
- * Enable Register.
+ * These are the EXTENDED definitions for the
+ * Exar 654's Interrupt Enable Register
*/
#define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */
#define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
@@ -74,8 +73,8 @@ struct cls_uart_struct {
#define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
#define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
-#define UART_EXAR654_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
-#define UART_EXAR654_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
+#define UART_EXAR654_XOFF_DETECT 0x1 /* Incoming XOFF char seen */
+#define UART_EXAR654_XON_DETECT 0x2 /* Incoming XON char seen */
#define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
#define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
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