Hi, Denis Carikli wrote: > If de-active and/or pixelclk-active properties were set in the > display-timings DT node, they were not used. > > Instead the data-enable and the pixel data clock polarity > were hardcoded. > > This change is needed for making the eukrea-cpuimx51 > QVGA display work. > I just tried this patch on our hardware and found that the pixelclock polarity is inverse to what the documentation says. Your patch sets the 'clk_pol' variable in positive logic, while it is interpreted in negative logic when converted to the final register value in drivers/staging/imx-drm/ipu-v3/ipu-di.c: if (!(sig->clk_pol)) di_gen |= DI_GEN_POLARITY_DISP_CLK; IMO this should be if (sig->clk_pol) di_gen |= DI_GEN_POLARITY_DISP_CLK; Did you actually measure the resulting clock signal and LCD data? Lothar Waßmann -- ___________________________________________________________ Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10 Geschäftsführer: Matthias Kaussen Handelsregistereintrag: Amtsgericht Aachen, HRB 4996 www.karo-electronics.de | info@xxxxxxxxxxxxxxxxxxx ___________________________________________________________ _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
