The "Counting Mode" registers are sequential in the enum ni_gpct_register. Replace this inline CamelCase function with a simple define. Signed-off-by: H Hartley Sweeten <hsweeten@xxxxxxxxxxxxxxxxxxx> Cc: Ian Abbott <abbotti@xxxxxxxxx> Cc: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/staging/comedi/drivers/ni_tio.c | 12 ++++++------ drivers/staging/comedi/drivers/ni_tio_internal.h | 16 +--------------- 2 files changed, 7 insertions(+), 21 deletions(-) diff --git a/drivers/staging/comedi/drivers/ni_tio.c b/drivers/staging/comedi/drivers/ni_tio.c index 21456d6..f791405 100644 --- a/drivers/staging/comedi/drivers/ni_tio.c +++ b/drivers/staging/comedi/drivers/ni_tio.c @@ -397,7 +397,7 @@ void ni_tio_init_counter(struct ni_gpct *counter) 0); if (ni_tio_counting_mode_registers_present(counter_dev)) { ni_tio_set_bits(counter, - NITIO_Gi_Counting_Mode_Reg(counter-> + NITIO_CNT_MODE_REG(counter-> counter_index), ~0, 0); } @@ -439,7 +439,7 @@ static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync) { struct ni_gpct_device *counter_dev = counter->counter_dev; const unsigned counting_mode_reg = - NITIO_Gi_Counting_Mode_Reg(counter->counter_index); + NITIO_CNT_MODE_REG(counter->counter_index); static const uint64_t min_normal_sync_period_ps = 25000; const uint64_t clock_period_ps = ni_tio_clock_period_ps(counter, ni_tio_generic_clock_src_select @@ -516,7 +516,7 @@ static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode) if (mode & NI_GPCT_INDEX_ENABLE_BIT) counting_mode_bits |= Gi_Index_Mode_Bit; ni_tio_set_bits(counter, - NITIO_Gi_Counting_Mode_Reg(counter-> + NITIO_CNT_MODE_REG(counter-> counter_index), Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask | Gi_Index_Mode_Bit, counting_mode_bits); @@ -582,7 +582,7 @@ int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger) break; } ni_tio_set_bits(counter, - NITIO_Gi_Counting_Mode_Reg + NITIO_CNT_MODE_REG (counter->counter_index), Gi_HW_Arm_Select_Mask (counter_dev->variant) | @@ -792,7 +792,7 @@ static int ni_tio_set_clock_src(struct ni_gpct *counter, break; } ni_tio_set_bits(counter, - NITIO_Gi_Counting_Mode_Reg(counter-> + NITIO_CNT_MODE_REG(counter-> counter_index), Gi_Prescale_X2_Bit(counter_dev->variant) | Gi_Prescale_X8_Bit(counter_dev->variant), @@ -807,7 +807,7 @@ static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter) { struct ni_gpct_device *counter_dev = counter->counter_dev; const unsigned counting_mode_bits = ni_tio_get_soft_copy(counter, - NITIO_Gi_Counting_Mode_Reg + NITIO_CNT_MODE_REG (counter-> counter_index)); unsigned bits = 0; diff --git a/drivers/staging/comedi/drivers/ni_tio_internal.h b/drivers/staging/comedi/drivers/ni_tio_internal.h index b8cd43b..0a4809a 100644 --- a/drivers/staging/comedi/drivers/ni_tio_internal.h +++ b/drivers/staging/comedi/drivers/ni_tio_internal.h @@ -28,21 +28,7 @@ #define NITIO_LOADA_REG(x) (NITIO_G0_LOADA + (x)) #define NITIO_LOADB_REG(x) (NITIO_G0_LOADB + (x)) #define NITIO_INPUT_SEL_REG(x) (NITIO_G0_INPUT_SEL + (x)) - -static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned idx) -{ - switch (idx) { - case 0: - return NITIO_G0_CNT_MODE; - case 1: - return NITIO_G1_CNT_MODE; - case 2: - return NITIO_G2_CNT_MODE; - case 3: - return NITIO_G3_CNT_MODE; - } - return 0; -} +#define NITIO_CNT_MODE_REG(x) (NITIO_G0_CNT_MODE + (x)) static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned idx) { -- 1.8.5.2 _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel