On Sun, Jul 15, 2018 at 12:34:28PM -0400, Jacob Feder wrote: > Hi, > I have updated this with the recommended changes. I haven't tried out the > UIO though. It will be a pretty significant undertaking and I don't want > to spend the time on it unless there is a specific reason you think it > will be faster. > > Thanks all. > > Cheers, > Jacob > > This IP core has read and write AXI-Stream FIFOs, the contents of which can > be accessed from the AXI4 memory-mapped interface. This is useful for > transferring data from a processor into the FPGA fabric. The driver creates > a character device that can be read/written to with standard > open/read/write/close. > > See Xilinx PG080 document for IP details. > > https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf > > The driver currently supports only store-forward mode with a 32-bit > AXI4 Lite interface. DOES NOT support: > - cut-through mode > - AXI4 (non-lite) > > Signed-off-by: Jacob Feder <jacobsfeder@xxxxxxxxx> > --- > Documentation/devicetree/bindings/axisfifo.txt | 89 ++ This should live in the directory with the driver until it gets accepted into the "main" part of the kernel tree. > drivers/staging/axisfifo/axis-fifo.c | 1242 ++++++++++++++++++++++++ > 2 files changed, 1331 insertions(+) > create mode 100644 Documentation/devicetree/bindings/axisfifo.txt > create mode 100644 drivers/staging/axisfifo/axis-fifo.c No Makefile or Kconfig to actually build the driver? Please fix that up so we can at least test-build the thing :) thanks, greg k-h _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
