This two functions are called with bus and func being always 0.
Remove non sensense 'bus' and 'func' parameters and pass '0' to
other calls inside the function. Review return and parameter types
also to be more proper with the rest of the code. Adapt properly
calls to those function to match the new prototypes.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 56 ++++++++++++++++-----------------
1 file changed, 27 insertions(+), 29 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index efcc008..c9da849 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -233,28 +233,26 @@ static struct pci_controller mt7621_controller = {
.io_resource = &mt7621_res_pci_io1,
};
-static void
-read_config(unsigned long bus, unsigned long dev, unsigned long func,
- unsigned long reg, unsigned long *val)
+static u32
+read_config(unsigned int dev, u32 reg)
{
u32 address_reg, data_reg, address;
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
- address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+ address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
writel(address, mt7621_pci_base + address_reg);
- *val = readl(mt7621_pci_base + data_reg);
+ return readl(mt7621_pci_base + data_reg);
}
static void
-write_config(unsigned long bus, unsigned long dev, unsigned long func,
- unsigned long reg, unsigned long val)
+write_config(unsigned int dev, u32 reg, u32 val)
{
u32 address_reg, data_reg, address;
address_reg = RALINK_PCI_CONFIG_ADDR;
data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
- address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+ address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
writel(address, mt7621_pci_base + address_reg);
writel(val, mt7621_pci_base + data_reg);
}
@@ -267,8 +265,8 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
int irq;
if (dev->bus->number == 0) {
- write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
- read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
+ write_config(slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+ val = read_config(slot, PCI_BASE_ADDRESS_0);
printk("BAR0 at slot %d = %x\n", slot, val);
}
@@ -409,7 +407,7 @@ void setup_cm_memory_region(struct resource *mem_resource)
static int mt7621_pci_probe(struct platform_device *pdev)
{
u32 mask;
- unsigned long val = 0;
+ u32 val;
mt7621_pci_base = (void __iomem *)RALINK_PCI_BASE;
iomem_resource.start = 0;
@@ -442,14 +440,14 @@ static int mt7621_pci_probe(struct platform_device *pdev)
bypass_pipe_rst();
set_phy_for_ssc();
- read_config(0, 0, 0, 0x70c, &val);
- printk("Port 0 N_FTS = %x\n", (unsigned int)val);
+ val = read_config(0, 0x70c);
+ printk("Port 0 N_FTS = %x\n", val);
- read_config(0, 1, 0, 0x70c, &val);
- printk("Port 1 N_FTS = %x\n", (unsigned int)val);
+ val= read_config(1, 0x70c);
+ printk("Port 1 N_FTS = %x\n", val);
- read_config(0, 2, 0, 0x70c, &val);
- printk("Port 2 N_FTS = %x\n", (unsigned int)val);
+ val = read_config(2, 0x70c);
+ printk("Port 2 N_FTS = %x\n", val);
rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
@@ -580,28 +578,28 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
switch (pcie_link_status) {
case 7:
- read_config(0, 2, 0, 0x4, &val);
- write_config(0, 2, 0, 0x4, val|0x4);
- read_config(0, 2, 0, 0x70c, &val);
+ val = read_config(2, 0x4);
+ write_config(2, 0x4, (val | 0x4));
+ val = read_config(2, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(0, 2, 0, 0x70c, val);
+ write_config(2, 0x70c, val);
case 3:
case 5:
case 6:
- read_config(0, 1, 0, 0x4, &val);
- write_config(0, 1, 0, 0x4, val|0x4);
- read_config(0, 1, 0, 0x70c, &val);
+ val = read_config(1, 0x4);
+ write_config(1, 0x4, (val | 0x4));
+ val = read_config(1, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(0, 1, 0, 0x70c, val);
+ write_config(1, 0x70c, val);
default:
- read_config(0, 0, 0, 0x4, &val);
- write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
- read_config(0, 0, 0, 0x70c, &val);
+ val = read_config(0, 0x4);
+ write_config(0, 0x4, (val | 0x4)); //bus master enable
+ val = read_config(0, 0x70c);
val &= ~(0xff)<<8;
val |= 0x50<<8;
- write_config(0, 0, 0, 0x70c, val);
+ write_config(0, 0x70c, val);
}
pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
--
2.7.4
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