Hi tglx, On 11/27/20 12:45 AM, Thomas Gleixner wrote: > Stefan, > > On Wed, Nov 25 2020 at 14:41, Stefan Bühler wrote: >> On 11/25/20 12:54 PM, Thomas Gleixner wrote: >>> On Wed, Sep 16 2020 at 12:12, Stefan Bühler wrote: >>> Can you please provide the output of: >>> >>> for ID in 05:00.0 06:00.0 06:00.1 06:01.0 06:01.1; do lspci -s $ID -vvv; done >> >> 05:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) >> ... >> Capabilities: <access denied> > > Can you please run this as root so the Capabilities are accessible? My bad, sorry. I did intend to run it as root, but should have checked the output. Again see attached file. While we're at it: the EEPROM for the PEX8112 is: 00000000 5a 03 3c 00 10 00 00 00 00 00 00 00 b5 10 12 81 |Z.<.............| 00000010 64 00 20 00 00 00 00 01 04 00 01 00 0c 10 00 fe |d. .............| 00000020 fe 03 20 10 f0 10 00 00 00 10 33 00 00 00 70 00 |.. .......3...p.| 00000030 00 00 11 00 48 00 00 00 00 00 34 00 50 00 00 00 |....H.....4.P...| 00000040 04 00 55 66 77 88 |..Ufw.| 00000046 (This is what the firmware tool provided to me writes, although I think the cards usually came pre-flashed with it. They gave me the tool because on some cards the second function on OX16PCI954 was sometimes uninitialized, came up with device id 0x9511 "8-bit bus" (PCI_DEVICE_ID_OXSEMI_16PCI95N) and the kernel tries to treat it as UART too.) I think some time ago I found a PDF to decode this here: https://www.broadcom.com/products/pcie-switches-bridges/pcie-bridges/pex8112#documentation But the broadcom site is completely broken right now (at least for me; there own search for "PEX 8112" links it, but then it says "not found"). Anyway, back then I decoded this to: - `0x5A 0x03`: Magic Header, contains register and shared memory settings - `0x003C` = 60 bytes for configs (10 registers): - `@0x0010`: `0x00000000` -- BAR0: Locate anywhere in 32-bit - `@0x0000`: `0x811210B5` -- Vendor `10B5`, Device `8112` (default) - `@0x0064`: `0x00000020` -- Device Capability: Enable "Support 8-bit Tag" field - `@0x0100`: `0x00010004` -- Power Budget Enhanced Capability Header (default) - `@0x100C`: `0x03FEFE00` -- PCI Control: - PCI-To-PCI Express Retry Count set to 0xFE (default: `0x80`) - PCI Express-to-PCI Retry Count set to 0xFE (default: `0x00`) - `@0x1020`: `0x000010F0` -- GPIO Control - GPIO[1-3] Output enable (GPIO[0] is Output enabled by default) - GPIO Diagnostic Select: `10b` (default: `01b`) - `@0x1000`: `0x00000033` -- Device Initialization (default) - `@0x0070`: `0x00110000` -- Link control: default - `@0x0048`: `0x00000000` -- Device-Specific Control (default 0) - `@0x0034`: `0x00000050` -- PCI Capability pointer `0x50` (default: `0x40`) - Skips (disables) Power Management Capability - Remaining: MSI and PCI Express - `0x0004` bytes for shared memory: - `0x55`, `0x66`, `0x77`, `0x88` TLDR: the most notable part probably being "disabling Power Management Capability" by the EEPROM. cheers, Stefan
05:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) Physical Slot: 1 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 16 NUMA node: 0 Bus: primary=05, secondary=06, subordinate=06, sec-latency=64 I/O behind bridge: 0000e000-0000efff Memory behind bridge: fb400000-fb4fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [60] Express (v1) PCI-Express to PCI/PCI-X Bridge, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0 ExtTag+ AttnBtn- AttnInd- PwrInd- RBE- SlotPowerLimit 26.000W DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- BrConfRtry- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100 v1] Power Budgeting <?> 06:00.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) (prog-if 06 [16950]) Subsystem: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 16 NUMA node: 0 Region 0: I/O ports at e0e0 [size=32] Region 1: Memory at fb407000 (32-bit, non-prefetchable) [size=4K] Region 2: I/O ports at e0c0 [size=32] Region 3: Memory at fb406000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 1 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0+,D1-,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: serial 06:00.1 Bridge: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled) Subsystem: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- NUMA node: 0 Region 0: I/O ports at e0a0 [disabled] [size=32] Region 1: Memory at fb405000 (32-bit, non-prefetchable) [disabled] [size=4K] Region 2: I/O ports at e080 [disabled] [size=32] Region 3: Memory at fb404000 (32-bit, non-prefetchable) [disabled] [size=4K] Capabilities: [40] Power Management version 1 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0+,D1-,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 06:01.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) (prog-if 06 [16950]) Subsystem: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 17 NUMA node: 0 Region 0: I/O ports at e060 [size=32] Region 1: Memory at fb403000 (32-bit, non-prefetchable) [size=4K] Region 2: I/O ports at e040 [size=32] Region 3: Memory at fb402000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 1 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0+,D1-,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: serial 06:01.1 Bridge: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled) Subsystem: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- NUMA node: 0 Region 0: I/O ports at e020 [disabled] [size=32] Region 1: Memory at fb401000 (32-bit, non-prefetchable) [disabled] [size=4K] Region 2: I/O ports at e000 [disabled] [size=32] Region 3: Memory at fb400000 (32-bit, non-prefetchable) [disabled] [size=4K] Capabilities: [40] Power Management version 1 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0+,D1-,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
