On 28/01/2020 16:53, Ionela Voinescu wrote: > Or you won't be able to access them at all. Lacking firmware support > accesses to AMU registers could be trapped in EL3. If access for EL1 and > EL2 is enabled from EL3, it's still possible that the counters > themselves are not enabled - that means they are not enabled to count > the events they are designed to be counting. That's why in this case the > event counter register could read 0. > > But if we read 0, it does not necessarily mean that the counter is > disabled. It could also mean that the events is meant to count did not > happen yet. > Right, which (as we discussed offline) is quite likely to happen if/when we get stuff like SVE counters and we try to read them at boot time. Might be worth adding a small note about that (0 != disabled). >> I haven't seen something that would try to catch this on the kernel side. >> Can we try to detect that (e.g. at least one counter returns > 0) in >> cpu_amu_enable() and thus not write to the CPU-local 'amu_feat'? >> > > I'm reluctant to do this especially given that platforms might choose to > keep some counters disabled while enabling some counters that might not > have counted any events by the time we reach cpu_enable. We would end up > mistakenly disabling the feature. I would rather leave the validation of > the counters to be done at the location and for the purpose of their > use: see patch 6/6 - the use of counters for frequency invariance. > Hmph, I'm a bit torn on that one. It would be really nice to provide *some* amount of sanity checking at core level - e.g. by checking that at least one of the four architected counters reads non-zero. But as you say these could be disabled, while some other arch/aux counter is enabled, and we could then mistakenly disable the feature. So we can't really do much unless we handle *each* individual counter. Oh well :/ >> While we're on the topic of detecting broken stuff, what if some CPUs >> implement some auxiliary counters that some others don't? >> > > I think it should be up to the user of that counter to decide if the > usecase is at CPU level or system level. My intention of this base > support was to keep it simple and allow users of some counters to > decide on their own how to validate and make use of either architected > or auxiliary counters. > > For example, in the case of frequency invariance, given a platform that > does not support cpufreq based invariance, I would validate all CPUs for > the use of AMU core and constant counters. If it happens that some CPUs > do not support those counters or they are not enabled, we'd have to > disable frequency invariance at system level. > > For some other scenarios only partial support is needed - only a subset > of CPUs need to support the counters for their use to be feasible. > > But I believe only the user of the counters can decide, whether this is > happening in architecture code, driver code, generic code. > Right, the FIE support is actually a good example of that, I think.
