On 18/12/2019 18:26, Ionela Voinescu wrote: > +Basic support > +------------- > + > +The kernel can safely run a mix of CPUs with and without support for the > +activity monitors extension. Therefore, when CONFIG_ARM64_AMU_EXTN is > +selected we unconditionally enable the capability to allow any late CPU > +(secondary or hotplugged) to detect and use the feature. > + > +When the feature is detected on a CPU, a per-CPU variable (amu_feat) is > +set, but this does not guarantee the correct functionality of the > +counters, only the presence of the extension. > + > +Firmware (code running at higher exception levels, e.g. arm-tf) support is > +needed to: > + - Enable access for lower exception levels (EL2 and EL1) to the AMU > + registers. > + - Enable the counters. If not enabled these will read as 0. Just to make sure I understand - if AMUs are physically present but not enabled by FW, we'll still - see them as implemented in ID_AA64PFR0_EL1.AMU - see some counters as available with e.g. AMCGCR_ELO.CG0NC > 0 But reading some AMEVCNTR<g><n> will return 0? > + - Save/restore the counters before/after the CPU is being put/brought up > + from the 'off' power state. > + > +When using kernels that have this configuration enabled but boot with > +broken firmware the user may experience panics or lockups when accessing > +the counter registers. Yikes > Even if these symptoms are not observed, the > +values returned by the register reads might not correctly reflect reality. > +Most commonly, the counters will read as 0, indicating that they are not > +enabled. If proper support is not provided in firmware it's best to disable > +CONFIG_ARM64_AMU_EXTN. > + I haven't seen something that would try to catch this on the kernel side. Can we try to detect that (e.g. at least one counter returns > 0) in cpu_amu_enable() and thus not write to the CPU-local 'amu_feat'? While we're on the topic of detecting broken stuff, what if some CPUs implement some auxiliary counters that some others don't? > +The fixed counters of AMUv1 are accessible though the following system > +register definitions: > + - SYS_AMEVCNTR0_CORE_EL0 > + - SYS_AMEVCNTR0_CONST_EL0 > + - SYS_AMEVCNTR0_INST_RET_EL0 > + - SYS_AMEVCNTR0_MEM_STALL_EL0 > + > +Auxiliary platform specific counters can be accessed using > +SYS_AMEVCNTR1_EL0(n), where n is a value between 0 and 15. > + > +Details can be found in: arch/arm64/include/asm/sysreg.h. > + > diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst > index 5d78a6f5b0ae..a3f1a47b6f1c 100644 > --- a/Documentation/arm64/booting.rst > +++ b/Documentation/arm64/booting.rst > @@ -248,6 +248,20 @@ Before jumping into the kernel, the following conditions must be met: > - HCR_EL2.APK (bit 40) must be initialised to 0b1 > - HCR_EL2.API (bit 41) must be initialised to 0b1 > > + For CPUs with Activity Monitors Unit v1 (AMUv1) extension present: > + - If EL3 is present: > + CPTR_EL3.TAM (bit 30) must be initialised to 0b0 > + CPTR_EL2.TAM (bit 30) must be initialised to 0b0 > + AMCNTENSET0_EL0 must be initialised to 0b1111 Nit: Or be a superset of the above, right? AIUI v1 only mandates the lower 4 bits to be set. Probably doesn't matter that much...
