On Mon, 21 Jul 2014, Ley Foon Tan wrote:
> On Tue, Jul 15, 2014 at 6:00 PM, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
>
> >> + count =
> >> + readw(timer_membase + ALTERA_TIMER_SNAPH_REG) << 16 |
> >> + readw(timer_membase + ALTERA_TIMER_SNAPL_REG);
> >
> > So you're serious about having a new architecture with a timer
> > implementation which cant read 32bit in one go? I'm impressed ...
> This is to compatible with 16-bit and 32-bit processors. The older
> version of Nios is 16-bit and Nios II is 32-bit.
> But this timer core doesn't get updated after Nios is end of life.
Sigh.
> >> +static cycle_t nios2_timer_read(struct clocksource *cs)
> >> +{
> >> + unsigned long flags;
> >> + u32 cycles;
> >> + u32 tcn;
> >> +
> >> + local_irq_save(flags);
> >> + tcn = NIOS2_TIMER_PERIOD - 1 - read_timersnapshot();
> >> + cycles = nios2_timer_count;
> >
> > This is wrong and completely pointless. The core code takes care about
> > the offset.
> This offset is different from the core code. The core code is handling
> cycle counter overlapping.
> But this is for the offset between last timer interrupt counter and
> current counter (read_timersnapshot()).
So IOW, if you ever lose a timer interrupt, your timekeeping is off by
a full cycle.
Great hardware design, really.
Thanks,
tglx
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